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PDF -10 



System Reference Manual 

7 J 5 gpgMHittKMtfttlitfg ' 



ORDER NO. DEC-10-HGAA-D FROM PROGRAM LIBRARY, MAYNARD, MASSACHUSETTS PRICE $5.00 

DIRECT COMMENTS CONCERNING THIS MANUAL TO SOFTWARE QUALITY CONTROL, MAYNARD, MASSACHUSETTS 

DIGITAL EQUIPMENT CORPORATION MAYNARD, MASSACHUSETTS 



April 1968 
Second printing, June 1968 



Changes are indicated by a 
triangle (A) in the outside margin. 



Copyright 1968 by 

Digital Equipment Corporation 



Instruction times, operating speeds and the like are 
included here for reference only; they are not to be 
taken as specifications. 



Written and designed for Digital Equipment Corporation by William English, Wayland, Massachusetts 
Manufactured in the United States of America 



Contents 



1 INTRODUCTION 1-1 

1.1 Number System 1-4 

Floating point arithmetic 1-5 

1.2 Instruction Format 1-6 

Effective address calculation 1-7 

1.3 Memory 1-8 

Memory allocation 1-9 

1.4 Programming Conventions 1-10 

2 CENTRAL PROCESSOR 2-1 

2. 1 Half Word Data Transmission 2-2 

2.2 Full Word Data Transmission 2-9 

Move instructions 2-10 
Pushdown list 2-12 

2.3 Byte Manipulation 2-15 

2.4 Logic 2-17 

Shift and rotate 2-24 

2.5 Fixed Point Arithmetic 2-26 

Arithmetic shifting 2-3 1 

2.6 Floating Point Arithmetic 2-32 

Scaling 2-33 

Operations with rounding 2-34 

Operations without rounding 2-37 

2.7 Arithmetic Testing 2-41 

2.8 Logical Testing and Modification 2-47 

2.9 Program Control 2-54 

2.10 Unimplemented Operations 2-64 

2. 1 1 Programming Examples 2-65 

Double precision floating point 2-67 

2.12 Input-Output 2-68 

Readin mode 2-72 
Console data transfers 2-73 



VI 



2.13 Priority Interrupt 2-73 

2.14 Processor Conditions 2-78 

3 BASIC IN-OUT EQUIPMENT 3-1 

3.1 Paper Tape Reader 3-1 

Readin mode 3-4 

3.2 Paper Tape Punch 3-5 

3.3 Teletype 3-7 

APPENDICES 

A Instruction and Device Mnemonics A 1 

Numeric listing A3 
Alphabetic listing A6 
Device mnemonics A10 

B In-out Codes Bl 

Teletype code B2 
Card codes B6 

C Miscellany Cl 



Introduction 



The PDF- 10 is a general purpose, stored program computer that includes a 
central processor, a memory, and a variety of peripheral equipment such as 
paper tape reader and punch, teletype, card reader, line printer, DECtape, 
magnetic tape, disk file and display. The central processor is the control unit 
for the entire system: it governs all peripheral in-out equipment, sequences 
the program, and performs all arithmetic, logical and data handling opera- 
tions. The processor is connected to one or more memory units by a mem- 
ory bus and to the peripheral equipment by an in-out bus. The fastest 
devices, such as the disc file, although controlled by the processor over the 
in-out bus, have direct access to memory over a second memory bus. 

The processor handles words of thirty-six bits, which are stored in a mem- 
ory with a maximum capacity of 262,144 words. Storage in memory is 
usually in the form of 37-bit words, the extra bit producingoddparit^ for 
the word. The bits of a word are numbered 0-35, left to right, as are the 
bits in the registers that handle the words. The processor can also handle 
half words, wherein the left half comprises bits 0-17, the right half, bits 
18-35. Optional hardware is available for byte manipulation a byte is any 
contiguous set of bits within a word. Registers that hold addresses have 
eighteen bits, numbered 18-35 according to the position of the address in a 
word. Words are used either as computer instructions in the program, as 
addresses, or as operands (data for the program). 

Of the internal registers shown in the illustration on the next page, only 
PC, the 18 bit program counter, is directly relevant to the programmer. The 
processor performs a program by executing instructions retrieved from the 
locations addressed by PC. At the beginning of each instruction PC is incre- 
mented by one so that it normally contains an address one greater than the 
location of the current instruction. Sequential program flow is altered by 
changing the contents of PC, either by incrementing it an extra time in a 
skip instruction or by replacing its contents with the value specified by a 
jump instruction. Also of importance to the programmer is the 36-bit data 
switch register DS on the processor console: through this register the pro- 
gram can read data supplied by the operator. The processor also contains 
flags that detect various types of errors, including several types of overflow 
in arithmetic and pushdown operations, and provide other information of 
interest to the programmer. 

The processor has other registers but the programmer is not usually con- 
cerned with them except when manually stepping through a program to 
debug it. By means of the address switch register AS, the operator can 

1-1 



1-2 



INTRODUCTION 



CORE MEMORY 

8192 OR 16384 
37-BIT WORDS 



CORE MEMORY 



CORE MEMORY 



MEMORY BUS 



FAST 
MEMORY 

16 X36 



MA 



18 



AS 



18 



PC 



18 



ARITHMETIC 
LOGIC 

(AR, BR, MQ) 



IN-OUT BUS 



CENTRAL 
PROCESSOR 



18 



Ml 



36 



DS 



36 



PRIORITY 
INTERRUPT 



PAPER TAPE 
READER 



PAPER TAPE 
PUNCH 



TELETYPE 



PDP-10 SIMPLIFIED 



examine the contents of, or deposit information into, any memory location; 
stop or interrupt the program whenever a particular location is referenced; 
and through AS the operator can supply a starting address for the program. 
Through the memory indicators MI the program can display data for the 
operator. The instruction register IR contains the left half of the current 
instruction word, ie all but the address part. The memory address register 
MA supplies the address for every memory access. The heart of the proc- 
essor is the arithmetic logic, principally the 36-bit arithmetic register AR. 



1-3 



This register takes part in all arithmetic, logical and data handling operations; 
all data transfers to and from memory, peripheral equipment and console are 
made via AR. Associated with AR are an extremely fast full adder, a buffer 
register BR that holds a second operand in many arithmetic and logical 
instructions, a multiplier-quotient register MQ that serves primarily as an 
extension of AR for handling double length operands, and smaller registers 
that handle floating point exponents and control shift operations and byte 
manipulation. 

From the point of view of the programmer however the arithmetic logic 
can be regarded as a black box. It performs almost all of the operations 
necessary for the execution of a program, but it never retains any informa- 
tion from one instruction to the next. Computations performed in the black 
box either affect control elements such as PC and the flags, or produce 
results that are always sent to memory and must be retrieved by the proc- 
essor if they are to be used as operands in other instructions. 

An instruction word has only one 18-bit address field for addressing any 
location throughout all of memory. But most instructions have two 4-bit 
fields for addressing the first sixteen memory locations. Any instruction 
that requires a second operand has an accumulator address field, which can 
address one of these sixteen locations as an accumulator; in other words as 
though it were a result held over in the processor from some previous 
instruction (the programmer usually has a choice of whether the result of the 
instruction will go to the location addressed as an accumulator or to that 
addressed by the 18-bit address field, or to both). Every instruction has a 
4-bit index register address field, which can address fifteen of these locations 
for use as index registers in modifying the 18-bit memory address (a zero 
index register address specifies no indexing). Although all computations on 
both operands and addresses are performed in the single arithmetic register 
AR, the computer actually has sixteen accumulators, fifteen of which can 
double as index registers. The factor that determines whether one of the 
first sixteen locations in memory is an accumulator or an index register is 
not the information it contains nor how its contents are used, but rather 
how the location is addressed. There need be no difference physically be- 
tween these locations and other memory locations, but an optional, fast flip- 
flop memory contained in the processor can be substituted for the bottom 
sixteen locations in core. This allows much quicker access to these locations 
whether they are addressed as accumulators, index registers or ordinary 
memory locations. They can even be addressed from the program counter, 
gaining faster execution for a short but oft-repeated subroutine. 

Besides the registers that enter into the regular execution of the program 
and its instructions, the processor has a priority interrupt system and can 
contain optional equipment to facilitate time sharing. The interrupt system 
facilitates processor control of the peripheral equipment by means of a num- 
ber of priority-ordered channels over which external signals may interrupt 
the normal program flow. The processor acknowledges an interrupt request 
by executing the instruction contained in a particular location assigned to 
the channel. Assignment of channels to devices is entirely under program 
control. One of the devices to which the program can assign a channel is the 
processor itself, allowing internal conditions such as overflow or a parity 



1-4 INTRODUCTION 1.1 

error to signal the program. 

The time share hardware provides memory protection and relocation. 
Without time sharing, all instructions and all memory are available to the 
program. Otherwise a number of programs share processor time, with each 
program relocated and restricted to a specific area in core, and certain in- 
structions are usually illegal. An attempt by any user to execute an illegal 
instruction or address a memory location outside of his area results in a 
transfer of control back to the time-sharing monitor. 



1.1 NUMBER SYSTEM 

The program can interpret a data word as a 36-digit, unsigned binary num- 
ber, or the left and right halves of a word can be taken as separate 1 8-bit 
numbers. The PDF- 1 repertoire includes instructions that effectively add 
or subtract one from both halves of a word, so the right half can be used for 
address modification when the word is addressed as an index register, while 
the left half is used to keep a control count. 

The standard arithmetic instructions in the PDF- 10 use twos comple- 
ment, fixed point conventions to do binary arithmetic. In a word used as a 
number, bit (the leftmost bit) represents the sign, for positive, 1 for 
negative. In a positive number the remaining 35 bits are the magnitude in 
ordinary binary notation. The negative of a number is obtained by taking its 
twos complement. If x is an -digit binary number, its twos complement is 
2"-x, and its ones complement is(2"-l)-jc, or equivalently (2"-x) - 1. 
Subtracting a number from 2"- 1 (ie, from all Is) is equivalent to perform- 
ing the logical complement, ie changing all Os to Is and all Is to Os. There- 
fore, to form the twos complement one takes the logical complement 
(usually referred to merely as the complement) of the entire word including 
the sign, and adds 1 to the result. In a negative number the sign bit is 1, and 
the remaining bits are the twos complement of the magnitude. 



+ 153, - +231 8 -000000000000000000000000000010011001 



35 



-153,0 = -231 8 =1111 111 111 111 111 111 111 111 111 101 100111 



35 

Zero is represented by a word containing all Os. Complementing this num- 
ber produces all Is, and adding 1 to that produces all Os again. Hence there 
is only one zero representation and its sign is positive. Since the numbers are 
symmetrical in magnitude about a single zero representation, all even num- 
bers both positive and negative end in 0, all odd numbers in 1 (a number all 
Is represents - 1). But since there are the same number of positive and nega- 
tive numbers and zero is positive, there is one more negative number than 
there are nonzero positive numbers. This is the most negative number and it 
cannot be produced by negating any positive number (its octal representa- 



1.1 



NUMBER SYSTEM 



1-5 



tion is 400000 000000 8 and its magnitude is one greater than the largest 
positive number). 

If ones complements were used for negatives one could read a negative 
number by attaching significance to the Os instead of the Is. In twos com- 
plement notation each negative number is one greater than the complement 
of the positive number of the same magnitude, so one can read a negative 
number by attaching significance to the rightmost 1 and attaching signifi- 
cance to the Os at the left of it (the negative number of largest magnitude has 
a 1 in only the sign position). In a negative integer, Is may be discarded at 
the left, just as leading Os may be dropped in a positive integer. In a negative 
fraction, Os may be discarded at the right. So long as only Os are discarded, 
the number remains in twos complement form because it still has a 1 that 
possesses significance; but if a portion including the rightmost 1 is discarded, 
the remaining part of the fraction is now a ones complement. 

The computer does not keep track of a binary point the programmer 
must adopt a point convention and shift the magnitude of the result to con- 
form to the convention used. Two common conventions are to regard a 
number as an integer (binary point at the right) or as a proper fraction 
(binary point at the left); in these two cases the range of numbers repre- 
sented by a single word is 2 35 to 2 35 - 1 or - 1 to 1 2~ 35 . Since multiplica- 
tion and division make use of double length numbers, there are special 
instructions for performing these operations with integral operands. 

Floating Point Arithmetic. Optional PDF- 1 hardware is available for 
processing floating point numbers. A floating point instruction interprets 
bit of a word as the sign, but interprets the rest of the word as an 8-bit 
exponent and a 27-bit fraction. For a positive number the sign is 0, as 
before. But the contents of bits 9-35 are now interpreted only as a binary 
fraction, and the contents of bits 1-8 are interpreted as an integral exponent 
in excess 128 (200 8 ) code. Exponents from -128 to +127 are therefore 
represented by the binary equivalents of to 255 (0-377 8 ). Floatingpoint 
zero and negatives are represented in exactly the same way as in fixed point: 
zero by a word containing all Os, a negative by the twos complement. A 
negative number has a 1 for its sign and the twos complement of the frac- 
tion, but since every fraction must ordinarily contain a 1 unless the entire 
number is zero (see below), it has the ones complement of the exponent 
code in bits 1-8. Since the exponent is in excess 128 code, an actual 
exponent x is represented in a positive number by x + 128, in a negative 
number by 127 -x. The programmer, however, need not be concerned with 
these representations as the hardware compensates automatically. Eg, for 

+ 153 10 = +231 8 = +.462 8 X2 8 - 






10001 


000 


100 


110 


010 


000 


000 


000 


000 


000 


000 



1 



8 9 



35 



-153 



10 



= -231. = -.462 R X2 8 = 



101 


110 111 


on 


001 


110 


000 


000 


000 


000 


000 


000 



Multiplication produces a 
double length product, and 
the programmer must remem- 
ber that discarding the low 
order part of a double length 
negative leaves the high order 
part in correct twos comple- 
ment form only if the low 
order part is null. 



o i 



8 9 



35 



1-6 



INTRODUCTION 



1.2 



the instruction that scales the exponent, the hardware interprets the integral 
scale factor in standard twos complement form but produces the correct 
ones complement result for the exponent. 

Except in special cases the floating point instructions assume that all non- 
zero operands are normalized, and they normalize a nonzero result. A 
floating point number is considered normalized if the magnitude of the frac- 
tion is greater than or equal to l /2 and less than 1 . These numbers thus have a 
fractional range in magnitude of 1 A. to 1 -2" 27 and an exponent range of 
- 1 28 to +127. The hardware may not give the correct result if the program 
supplies an operand that is not normalized or that has a zero fraction with a 
nonzero exponent. 

The precaution about truncation given for fixed point multiplication 
applies to all floating point operations as they all produce extra length 
results; but here the programmer may request rounding, which automatically 
restores the high order part to twos complement form if it is negative. In 
division the two words of the result are quotient and remainder, but in the 
other operations they form a double length number which is stored in two 
accumulators if the instruction is executed in "long" mode. This number 
contains a 54-bit fraction, half of which is in bits 9-35 of each word. The 
sign and exponent are in bits and 1 -8 respectively of the word containing 
the more significant half, and the standard twos complement is used to form 

In the remaining part of the less 



8 contain a number 27 less than the 
exponent, but this is expressed in positive form even though bits 9-35 may 
be part of a negative fraction. Eg the number 2 18 + 2~ 18 has this two-word 
representation: 



010 


010 


on 


100 


000 


000 


000 


000 


000 


000 


000 


000 



1 



8 9 



35 



001 


1 1 1 000 


000 


000 


000 


100 


000 


000 


000 


000 


000 



1 



8 9 



35 



whereas its negative is 



101 


101 


100 


on 


111 111 111 111 111 1 


1 111 111 



1 



8 9 



35 



001 111 OOOll 11 111 111 100 000 000 000 000 000 




35 



.2 INSTRUCTION FORMAT 



In all but the input-output instructions, the nine high order bits (0-8) speci- 
fy the operation, and bits 9-12 usually address an accumulator but are 
sometimes used for special control purposes, such as addressing flags. The 



1.2 



INSTRUCTION FORMAT 



1-7 



rest of the instruction word usually supplies information for calculating the 
effective address, which is the actual address used to fetch the operand or 
alter program flow. Bit 13 specifies the type of addressing, bits 14-17 spec- 
ify an index register for use in address modification, and the remaining 
eighteen bits (18-35) address a memory location. The instruction codes 



ADDRESS TYPE 



ACCUMULATOR 
ADDRESS \ 



INDEX REGISTER 
ADDRESS 



INSTRUCTION CODE 


\ 




/ 


MEMORY ADDRESS 



89 121314 1718 

BASIC INSTRUCTION FORMAT 



35 



that are not assigned as specific instructions are executed by the processor 
as so-called "unimplemented operations", as are the codes for floating point 
and byte manipulation in any PDF- 1 that does not have the optional hard- 
ware for these instructions. When the processor encounters one of these 
unimplemented codes in a program, it stores bits 0-12 of the instruction 
word and the calculated effective address in a particular memory location 
and then executes the instruction contained in a second location. 

An input-output instruction is designated by three Is in bits 0-2. Bits 
3-9 address the in-out device to be used in executing the instruction, and 
bits 10-12 specify the operation. The rest of the word is the same as in 
other instructions. 



INSTRUCTION 
/ CODE \ 



ADDRESS TYPE 

INDEX REGISTER 
/ ADDRESS 



7 


DEVICE CODE 






/ 


MEMORY ADDRESS 



23 



910 121314 1718 

IN-OUT INSTRUCTION FORMAT 



35 



Effective Address Calculation. Bits 13-35 have the same format in every 
instruction whether it addresses a memory location or not. Bit 13 is the 



I 


X 


Y 



13 14 



17 18 



35 




indirect bit, bits 14-17 are the index register address, and if the instruction 
must reference memory, bits 18-35 are the memory address Y. The 
tive address E of the instruction depends on the values of/, X and Y^lf X is 
nonzero, the contents of index register X are added to Y to produce a modi- 
fied address. If / is 0, addressing is direct, and the modified address is the 
effective address used in the execution of the instruction; if / is 1 , addressing 
is indirect, and the processor retrieves another address word from the loca- 
tion specified by the modified address already determined. This new word is 
processed in exactly the same manner: X and Y determine the effective ad- 
dress if / is 0, otherwise they are used for yet another level of address 



^p 
V 



1-8 INTRODUCTION 1.3 

retrieval. This process continues until some referenced location is found 
with a in bit 13; the 18-bit number calculated from the X and Y parts of 
this location is the effective address E. 

The calculation outlined above is carried out for every instruction even 
if it need not address a memory location. If the indirect bit in the instruc- 
tion word is and no memory reference is necessary, then Y is not an ad- 
dress. It may be a mask in some kind of test instruction, conditions to be 
sent to an in-out device, or part of it may be the number of places to shift in 
a shift or rotate instruction or the scale factor in a floating scale instruction. 
Even when modified by an index register, bits 18-35 do not contain an ad- 
dress when / is 0. But when / is 1, the number determined from bits 14-35 
is an indirect address no matter what type of information the instruction 
requires, and the word retrieved in any step of the calculation contains an 
indirect address so long as / remains 1 . When a location is found in which / 
is 0, bits 18-35 (perhaps modified by an index register) contain the desired 
effective mask, effective conditions, effective shift number, or effective scale 
factor. Many of the instructions that usually reference memory for an oper- 
and even have an "immediate" mode in which the result of the effective 
address calculation is itself used as a half word operand instead of a word 
taken from the memory location it addresses. 

The important thing for the programmer to remember is that the same 
calculation is carried out for every instruction regardless of the type of infor- 
mation that must be specified for its execution, or even if the result is 
ignored. In the discussion of any instruction, E refers to the actual quantity 
derived from /, X and Y and used in the execution of the instruction, be it 
the entire half word as in the case of an address, immediate operand, mask or 
conditions, or only part of it as in a shift number or scale factor. 



1.3 MEMORY 

All timing in the PDF- 10 is asynchronous. The internal timing for each in- 
out device and each memory is entirely independent of the central processor. 
Because core memory readout is destructive, every word read must be writ- 
ten back in unless new information is to take its place. The basic read-write 
cycle time of the standard core memory is either 1 .00 or 1 .65 microseconds, 
but the processor need never wait the entire cycle time. To read, it waits 
only until the information is available and then continues its operations 
while the memory performs the write portion of the cycle; to write, it waits 
only until the data is accepted, and the memory then performs an entire 
cycle to clear and write. To save time in an instruction that fetches an oper- 
and and then writes new data into the same location, the memory executes a 
read-pause-write cycle in which it performs only the read part initially and 
then completes the cycle when the processor supplies the new data. 

Access times for the accumulator-index register locations are decreased 
considerably by substitution of a fast memory (contained in the processor) 
for the first sixteen core locations. Readout is nondestructive, so the fast 
memory has no basic cycle: the processor reads a word directly, but to write 



1-3 



MEMORY 



1-9 



it must first clear the location and then load it. Access times in nanoseconds 
(including 20 feet of cable delay) for the three memories are as follows. 



MA 1 or MA 1 OA Core Memory ( 1 .00 jus) 

MB 1 Core Memory ( 1 .65 jus) 

KM 10 Fast Memory ( 1 8-bit address) 



Read 
550 

600 (700)* 
210 



Write 

200 

200 (300) 

210 



NOTE: When a fast memory location is addressed as an accumulator or index 
register, the access time is usually considerably shorter than that listed here. 

From the simple addressing point of view, the entire memory is a set of 
contiguous locations whose addresses range from zero to a maximum 
dependent upon the capacity of the particular installation. In a system with 
the greatest possible capacity, the largest address is octal 777777 ', decimal 
262,143. (Addresses are always in octal notation unless otherwise specified.) 
But the whole memory would usually be made up of a number of core mem- 
ories each having a capacity of 8192 or 16,384 words. Hence a single 18-bit 
address actually selects a particular memory and a specific location within it. 
For an 8K memory the high order five address bits select the memory, the 
remaining thirteen bits address a single location in it; selecting a 16K 
memory takes four bits, leaving fourteen for the location. The times given 
above assume the addressed memory is idle when access is requested. To 
avoid waiting for a previously requested memory cycle to end, the program 
can make consecutive requests to different memories by taking instructions 
from one memory and data from another. The hardware also allows pairs 
of memories to be interleaved in such a way that consecutive addresses 
actually alternate between the two memories in the pair (thus increasing the 
probability that consecutive references are to different memories). Appro- 
priate switch settings at the memories interchange the least significant 
address bits in the memory and location parts, so that in any two memories 
numbered n and n + 1 where n is even, all even addresses are locations in the 
first memory, all odd addresses are locations in the second. Hence memories 
and 1 can be interleaved as can 6 and 7, but not 3 and 4 or 5 and 7. 

Memory Allocation. The use of certain memory locations is defined by 
the hardware. 

Holds a pointer word during a bootstrap readin 

0-17 Can be addressed as accumulators 

1-17 Can be addressed as index registers 

40-41 Trap for unimplemented user operations (UUOs) 

42-57 Priority interrupt locations 

60-61 Trap for remaining unimplemented operations: these include 

the unassigned instruction codes that are reserved for future 
use, and also the byte manipulation and floating point instruc- 
tions when the hardware for them is not installed 

140-161 Allocated to second processor if connected (same use as 40-61 
for first processor) 



*Numbers in parentheses are 
the longer times required in 
a multiprocessor system. 



All information given in this 
manual about memory loca- 
tions 40-61 applies instead 
to locations 140-161 for pro- 
gramming a second central 
processor connected to the 
same memory. 

The initial control word 
address for the DF10 Data 
Channel must be less than 
1000. 



1-10 



INTRODUCTION 



1.4 



The assembler translates 
every statement into a 36-bit 
word, placing Os in all bits 
whose values are unspecified. 



1.4 PROGRAMMING CONVENTIONS 

The computer has five instruction classes: data transmission, logical, arith- 
metic, program control and in-out. The instructions in the in-out class con- 
trol the peripheral equipment, and also control the priority interrupt and 
time sharing, control and read the processor flags, and communicate with the 
console. The next chapter describes all instructions mentioned above, 
presents a general description of input-output, and describes the effects of 
the in-out instructions on the processor, priority interrupt and time share 
hardware. Effects of in-out instructions on particular peripheral devices are 
discussed with the devices. 

The MACRO-IO assembly program recognizes a number of mnemonics and 
other initial symbols that facilitate constructing complete instruction words 
and organizing them into a program. In particular there are mnemonics for 
the instruction codes (Appendix A), which are six bits in in-out instructions, 
otherwise nine or thirteen bits. Eg the mnemonic 

MOVNS 

assembles as 213000 000000, and 
MOVNS 2570 

assembles as 213000 002570. This latter word, when executed as an instruc- 
tion, produces the twos complement negative of the word in memory loca- 
tion 2570. 



NOTE 

Throughout this manual all numbers representing instruction words, 
register contents, codes and addresses are always octal, and any num- 
bers appearing in program examples are octal unless otherwise indi- 
cated. On the other hand, the ordinary use of numbers in the text to 
count steps in an operation or to specify word or byte lengths, bit 
positions, exponents, etc employs standard decimal notation. 

The initial symbol @ preceding a memory address places a 1 in bit 13 to 
produce indirect addressing. The example given above uses direct addressing, 
but 

MOVNS @2570 

assembles as 213020 002570, and produces indirect addressing. Placing the 
number of an index register (1-17) in parentheses following the memory 
address causes modification of the address by the contents of the specified 
register. Hence , 

MOVNS @2570(12) 

which assembles as 213032 002570, produces indexing using index register 
12, and the processor then uses the modified address to continue the effec- 
tive address calculation. 

An accumulator address (0- 1 7) precedes the memory address part (if any) 



1 .4 PROGRAMMING CONVENTIONS 1-11 

and is terminated by a comma. Thus 
MOVNS 4,@2570(12) 

assembles as 213232 002570, which negates the word in location E and 
stores the result in both E and in accumulator 4. The same procedure may 
be used to place Is in bits 9-12 when these are used for something other 
than addressing an accumulator, but mnemonics are available for this pur- 
pose. 

The device code in an in-out instruction is given in the same manner as an 
accumulator address (terminated by a comma and preceding the address 
part), but the number given must correspond to the octal digits in the word 
(000-774). Mnemonics are however available for all standard device codes. 
To control the priority interrupt system whose code is 004, one may give 

CONO 4,1302 

which assembles as 700600 0001302, or equivalently 
CONO PI, 1302 

The programming examples in this manual use the following addressing 
conventions: 

* A colon following a symbol indicates that it is a symbolic location name. 

A: ADD 6,5704 

indicates that the location that contains ADD 6,5704 may be addressed sym- 
bolically as A. 

* The period represents the current address, eg 

ADD 5, .+2 
is equivalent to 
A: ADD 5,A+2 

4 Square brackets specify the contents of a location, leaving the address of 
the location implicit but unspecified. Eg 

ADD 12,[7256004] 
and 

ADD 12, A 



A: 7256004 

are equivalent. 

Anything written at the right of a semicolon is commentary that explains 
the program but is not part of it. 



Central Processor 



This chapter describes all PDF- 10 instructions but does not discuss the 
effects of those in-out instructions that address specific peripheral devices. 
In the description of each instruction, the mnemonic and name are at the 
top, the format is in a box below them. The mnemonic assembles to the 
word in the box, where bits in those parts of the word represented by letters 
assemble as Os. The letters indicate portions that must be added to the mne- 
monic to produce a complete instruction word. 

For many of the non-IO instructions, a description applies not to a unique 
instruction with a single code in bits 0-8, but rather to an instruction set 
defined as a basic instruction that can be executed in a number of modes. 
These modes define properties subsidiary to the basic operation; eg in data 
transmission the mode specifies which of the locations addressed by the in- 
struction is the source and which the destination of the data, in test instruc- 
tions it specifies the condition that must be satisfied for a jump or skip to 
take place. The mnemonic given at the top is for the basic mode; mnemonics 
for the other forms of the instruction are produced by appending letters 
directly to the basic mnemonic. Following the description is a table giving 
the mnemonics and octal codes (bits 0-8) for the various modes. 

The processor execution time for each instruction is also given at the top 
unless the time differs from one mode to another. The time listed is that 
required for direct addressing without indexing (ie with no effective address 
calculation), assuming the instruction and location E are both in the same 
1.00 microsecond core memory, and that an accumulator is addressed only 
if necessary and is in fast memory. The time that can be saved (if any) by 
interleaving or keeping instructions and operands in different memories is 
indicated either with the description or with the discussion of the modes 
preceding a group of instructions. To determine the exact time required for 
an instruction under any circumstances, refer to the timing chart in 
Appendix C. 

In a description E refers to the effective address, half word operand, mask, 
conditions, shift number or scale factor calculated from the /, X and Y parts 
of the instruction word. In an instruction that ordinarily references mem- 
ory, a reference to E as the source of information means that the instruction 
retrieves the word contained in location E; as a destination it means the in- 
struction stores a word in location E. In the immediate mode of these 
instructions, the effective half word operand is usually treated as a full word 
that contains E in one half and zero in the other, and is represented either as 
0,E or ,0 depending upon whether E is in the right or left half. 

2-1 



Letters representing modes 
are suffixes, which produce 
new mnemonics that are rec- 
ognized as distinct symbols 
by the assembler. 



2-2 CENTRAL PROCESSOR 2.1 

Most of the non-IO instructions can address an accumulator, and in the 
box showing the format this address is represented by A ; in the description, 
"AC" refers to the accumulator addressed by A . "AC left" and "AC right" 
refer to the two halves of AC. If an instruction uses two accumulators, these 
have addresses A and ,4 + 1, where the second address is if A is 17. In some 
cases an instruction uses an accumulator only if A is nonzero: a zero address 
in bits 9-12 specifies no accumulator. 

It is assumed throughout that time sharing is not in effect, and the pro- 
gram is unrestricted. For completeness, however, the effects of restrictions 
on particular instructions are noted; and execution times are given both for 
unrestricted operation and t including relocation in a user program (the latter 
jtime is given in parentheses). 2.15 lists all restrictions on user programs 
and explains the special effects produced by certain instructions when exe- 
cuted under control of the monitor while the processor is in user mode. 

Some simple examples are included with the instruction descriptions, but 
more complex examples using a variety of instructions are given in 2. 1 1. 



2.1 HALF WORD DATA TRANSMISSION 

These instructions move a half word and may modify the contents of the 
other half of the destination location. There are sixteen instructions deter- 
mined by which half of the source word is moved to which half of the des- 
tination, and by which of four possible operations is performed on the other 
half of the destination. The basic mnemonics are three letters that indicate 
the transfer 

HLL Left half of source to left half of destination 

HRL Right half of source to left half of destination 

HRR Right half of source to right half of destination 

HLR Left half of source to right half of destination 

plus a fourth, if necessary, to indicate the operation. 

Operation Suffix Effect on Other Half of Destination 

Do nothing None 

Zeros Z Places Os in all bits of the other half 

Ones O Places Is in all bits of the other half 

Extend E Jlgces_Jh dgn rthp leftmost b,jt) nf 

Qie half word mnvpfl in all bits pf tjv' 
other half. This action extends a right 
half word number into a full word 
number but is valid arithmetically 
only for positive left half word num- 
bers the right extension of a number 
requires Os regardless of sign (hence 
the Zeros operation should be used to 
extend a left half word number). 



2.1 



HALF WORD DATA TRANSMISSION 



2-3 



An additional letter may be appended to indicate the mode, which deter- 
mines the source and destination of the half word moved. 



Mode 


Suffix 


Source 


Destination 


Basic 




E 


AC 


Immediate 


I 


The word 0,E 


AC 


Memory 


M 


AC 


E 


Self 


S 


E 


E, but also AC 








if A is nonzero 



Note that selecting the left half of the source in immediate mode merely 
clears the selected half of the destination. 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) /us in self 
mode; in memory mode the 
same saving results if no ac- 
tion is taken on the other 
half, otherwise .47 (.36) /us 
is saved. 

When E addresses a fast 
memory location, a half word 
transfer takes .34 /us less in 
basic mode, either. .46 (.35) 
or .54 (.43) /us less in memory 
mode depending respectively 
on whether or not any action 
is taken on the other half, 
and .54 (.43) /us less in self 
mode. 



HLL 



Half Word Left to Left 



500 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination. The source and the destination right half are un- 
affected; the original contents of the destination are lost. 



HLL Half Left to Left 

HLLI Half Left to Left Immediate 

H L LM Half Left to Left Memory 

HLLS Half Left to Left Self 



500 2.35 (2.57) /us 

501 1.50(1.61)jus 

502 2.90 (3.01) MS 

503 2.76 (2.87) MS 



HLLI merely clears AC left. 
If A is zero, HLLS is a no-op, 
otherwise it is equivalent to 
HLL. 



HLLZ 



Half Word Left to Left, Zeros 



5 10 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination, and clear the destination right half. The source is un- 
affected, the original contents of the destination are lost. 



HLLZ Half Left to Left, Zeros 

HLLZI Half Left to Left, Zeros, Immediate 

HLLZM Half Left to Left, Zeros, Memory 

HLLZS Half Left to Left, Zeros, Self 



510 
2.21 (2.43) MS 

511 
1.36 (1.47) MS 

512 
2.47 (2.58) MS 

513 
2.76 (2.87) MS 



HLLZI merely clears AC. If A 
is zero, HLLZS merely clears 
the right half of location E. 



2-4 



HLLOI sets AC to all Os in 
the left half, all Is in the 
right. 



HLLO 



CENTRAL PROCESSOR 

Half Word Left to Left, Ones 



2.1 



520 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination, and set the destination right half to all 1 s. The source 
is unaffected, the original contents of the destination are lost. 



HLLO Half Left to Left, Ones 

HLLOI Half Left to Left, Ones, Immediate 

HLLOM Half Left to Left, Ones, Memory 

HLLOS Half Left to Left, Ones, Self 



520 
2.21 (2.43) MS 

521 
1.36 (1.47) MS 

522 
2.47 (2. 58) MS 

523 
2. 76 (2. 87) MS 



HLLEI is equivalent to 
HLLZI (it merely clears AC). 



HLLE 



530 



Half Word Left to Left, Extend 



M 



X 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination, and make all bits in the destination right half equal to 
bit of the source. The source is unaffected, the original contents of the 
destination are lost. 



HLLE Half Left to Left, Extend 

HLLEI Half Left to Left, Extend, Immediate 

HLLEM Half Left to Left, Extend, Memory 

HLLES Half Left to Left, Extend, Self 



530 
2.21 (2.43) MS 

531 
1.36 (1.47) MS 

532 
2.47 (2.58) MS 

533 
2. 76 (2.87) MS 



HRL 



Half Word Right to Left 



504 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the left half of the 
specified destination. The source and the destination right half are unaf- 
fected; the original contents of the destination left half are lost. 



HRL Half Right to Left 504 

H R LI Half Right to Left Immediate 505 



2. 70 (2.92) MS 
1.85 (1.96) MS 



2.1 



HALF WORD DATA TRANSMISSION 



2-5 



H R LM Half Right to Left Memory 

H R LS Half Right to Left Self 



506 2.90 (3.01) MS 

507 2.76 (2.87) jus 



HRLZ 



Half Word Right to Left, Zeros 



5 14 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



HRLZ 
HRLZI 
HRLZM 
HRLZS 



Move the right half of the source word specified by M to the left half of the 
specified destination, and clear the destination right half. The source is un- 
affected, the original contents of the destination are lost. 

Half Right to Left, Zeros 5 1 4 

2.21 (2.43) /xs 

Half Right to Left, Zeros, Immediate 5 1 5 

1.36 (1.47) MS 

Half Right to Left, Zeros, Memory 5 1 6 

2.47 (2.58) /as 

Half Right to Left, Zeros, Self 5 1 7 

2.76 (2.87) MS 



HRLZI loads the word ",0 
into AC. 



HRLO 



Half Word Right to Left, Ones 



524 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the left half of the 
specified destination, and set the destination right half to all Is. The source 
is unaffected, the original contents of the destination are lost. 



HRLO Half Right to Left, Ones 

HRLO I Half Right to Left, Ones, Immediate 

HRLOM Half Right to Left, Ones, Memory 

H R LOS Half Right to Left, Ones, Self 



524 
2.21 (2.43) MS 

525 
1.36 (1.47) MS 

526 
2.47 (2.58) MS 

527 
2.76 (2.87) MS 



HRLE 



Half Word Right to Left, Extend 



534 


M 


A 


I 


X 


Y 



67 89 121314 1718 35 

Move the right half of the source word specified by M to the left half of the 



2-6 



CENTRAL PROCESSOR 



2.: 



specified destination, and make all bits in the destination right half equal to 
bit 18 of the source. The source is unaffected, the original contents of the 
destination are lost. 



H R L E Half Right to Left , Extend 

HRLEI Half Right to Left, Extend, Immediate 

H R LEM Half Right to Left, Extend, Memory 

HRLES Half Right to Left, Extend, Self 



534 
2.21 (2.43) jus 

535 
1.36 (1.47) MS 

536 
2.47 (2.58) MS 

537 
2.76 (2.87) MS 



If A is zero, HRRS is a no-op; 
otherwise it is equivalent to 
HRR. 



HRR 



Half Word Right to Right 



540 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination. The source and the destination left half are unaffected; 
the original contents of the destination right half are lost. 



HRR Half Right to Right 540 

H R R I Half Right to Right Immediate 54 1 

HRRM Half Right to Right Memory 542 

HRRS Half Right to Right Self 543 



2.35 (2.57) MS 
1.50(1.61)MS 
2.90 (3.01) MS 
2.76 (2.87) MS 



HRRZI loads the word 0,^ 
into AC. If A is zero, HRRZS 
merely clears the left half of 
location E. 



HRRZ 



Half Word Right to Right, Zeros 



550 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination, and clear the destination left half. The source is unaf- 
fected, the original contents of the destination are lost. 



HRRZ Half Right to Right, Zeros 

HRRZI Half Right to Right, Zeros, Immediate 

H R RZM Half Right to Right, Zeros, Memory 

H R RZS Half Right to Right, Zeros, Self 



550 
2.21 (2.43) MS 

551 
1.36 (1.47) MS 

552 
2.47 (2.58) MS 

553 
2.76 (2.87) MS 



2.1 



HALF WORD DATA TRANSMISSION 



2-7 



HRRO Half Word Right to Right, Ones 



560 


M 


A 


I 


X 


Y 


67 89 12 


1314 17 


18 35 


Move the right 


half of the source word specified by M to the right half of the 


specified destination, and set 


the destination left half to all Is. The source is 


unaffected, the original contents of the destination are lost. 


HRRO Half Right to Right, Ones 560 












2.21 (2.43) MS 


H R R 1 Half Right to Right, Ones 


.Immediate 561 












1.36 (1.47) MS 


HRROM Half Right to Right, Ones 


, Memory 562 












2.47 (2.58) jus 


HRROS Half Right to Right, Ones, Self 563 












2.76 (2.87) MS 


HRRE Half Word Right to 


Right, Extend 


570 


M 


A 


/ 


X 


Y 


67 89 12 


13 


14 17 


18 35 


Move the right 


half of the source word 


specified by M to the right half of the 


specified destination, and make all bits in the destination left half equal to 


bit 18 of the source. The source is unaffected, the original contents of the 


destination are 


lost 








- 


HRRE Half Right to Right, Extend 570 












2.21 (2.43) MS 


HRREI Half Right to Right, Extend, Immediate 571 












1.36 (1.47) MS 


HRREM Half Right to Right, Extend, Memory 572 












2.47 (2.58) MS 


HRRES Half Right to Right, Extend, Self 573 












2.76 (2.87) MS 


HLR Half Word Left to Right 


544 


M 


A 


/ 


X 


Y 



67 89 



121314 1718 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination. The source and the destination left half are unaffected; 
the original contents of the destination right half are lost. 

HLR Half Left to Right 544 2.70 (2.92) MS 

HLRI Half Left to Right Immediate 545 1.85 (1.96) MS 



HLRI merely clears AC right. 



2-8 



CENTRAL PROCESSOR 



HLRM Half Left to Right Memory 

HLRS Half Left to Right Self 



2.1 



546 

547 



2.90 (3.01) 

2.76 (2.87) 



HLRZI merely clears AC and 
is thus equivalent to HLLZI. 



HLRZ 



Half Word Left to Right, Zeros 



554 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination, and clear the destination left half. The source is un- 
affected, the original contents of the destination are lost. 



HLRZ Half Left to Right, Zeros 

HLRZI Half Left to Right, Zeros, Immediate 

HLRZM Half Left to Right, Zeros, Memory 

HLRZS Half Left to Right, Zeros, Self 



554 
2.21 (2.43) MS 

555 
1.36 (1.47) MS 

556 
2.47 (2.58) MS 

557 
2.76 (2.87) MS 



HLROI sets AC to all Is in 
the left half, all Os in the 

right. 



HLRO 



564 



Half Word Left to Right, Ones 



M 



X 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination, and set the destination left half to all Is. The source is 
unaffected, the original contents of the destination are lost. 



HLRO Half Left to Right, Ones 

HLROI Half Left to Right, Ones, Immediate 

HLROM Half Left to Right, Ones, Memory 

HLROS Half Left to Right, Ones, Self 



564 
2.21 (2.43) MS 

565 
1.36 (1.47) MS 

566 
2.47 (2.58) MS 

567 
2.76 (2.87) MS 



HLRE 



Half Word Left to Right, Extend 



574 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination, and make all bits in the destination left half equal to 



2.2 



FULL WORD DATA TRANSMISSION 



2-9 



bit of the source. The source is unaffected, the original contents of the 
destination are lost. 



HIRE Half Left to Right, Extend 

HLREI Half Left to Right, Extend, Immediate 

HLREM Half Left to Right, Extend, Memory 

HIRES Half Left to Right, Extend, Self 



574 
2.21 (2.43) MS 

575 
1.36 (1.47) /is 

576 
2.47 (2.58) jus 

577 
2.76 (2.87) MS 



HLREI is equivalent to 
HLRZI (it merely clears AC). 



EXAMPLES. The half word transmission instructions are very useful for 
handling addresses, and they provide a convenient means of setting up an 
accumulator whose right half is to be used for indexing while a control count 
is kept in the left half. Eg this pair of instructions loads the 18-bit numbers 
M and N into the left and right halves respectively of an accumulator that is 
addressed symbolically as XR. 



HRLZI 
HRRI 



XR,M 
XR,N 



Of course the source program must somewhere define the value of the 
symbol XR as an octal number between 1 and 17. 

Suppose that at some point we wish to use the two halves of XR inde- 
pendently as operands (taken as 18-bit positive numbers) for computations. 
We can begin by moving XR left to the right half of another accumulator 
AC and leaving the contents of XR right alone in XR. 



HLRZM 
HLLI 



XR,AC 
XR, 



;Clear XR left 



It is not necessary to clear the 
other half of XR when load- 
ing the first half word. But 
any instruction that modifies 
the other half is faster than 
the corresponding instruction 
that does not, as the latter 
must fetch the destination 
word in order to save half of 
it. (The difference does not 
apply to self mode, for here 
the source and destination are 
the same.) 



2.2 FULL WORD DATA TRANSMISSION 

These are the instructions whose basic purpose is to move one or more full 
words of data from one place to another, usually from an accumulator to a 
memory location or vice versa. In a few cases instructions may perform 
minor arithmetic operations, such as forming the negative or the magnitude 
of the word being processed. 



EXCH 



Exchange 



2.90 (3.01) MS 



250 


A 


I 


X 


Y 



89 121314 1718 35 

Move the contents of location E to AC and move AC to location E. 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) /us. 



2-10 



CENTRAL PROCESSOR 



2.2 



The time depends on the 
number and type of trans- 
fers. Assuming at least one 
word is moved a BLT takes 
.97 (1.08) MS plus 2.26 (2.48) 
jus per transfer from fast 
memory to core and 2.61 
(2.83) us per transfer from 
core to fast memory or from 
one core location to another. 



BLT 



Block Transfer 



25 1 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Beginning at the location addressed by AC left, move words to another area 
of memory beginning at the location addressed by AC right. Continue until 
a word is moved to location E. The total number of words in the block is 
thus E - AC R + 1 . 







CAUTION 

Priority interrupts are allowed during the execution of this instruction, 
following the processing of each word. If an interrupt occurs, the BLT 
stores the source and destination addresses for the next word in AC, so 
when the processor restarts upon the return to the interrupted program, 
it actually resumes at the correct point within the BLT. Therefore, 
unless the interrupt system is inactive, A and X must not address the 
same register as this would produce a different effective address calcula- 
tion upon resumption should an interrupt occur; and the program must 
not attempt to load an accumulator addressed either by A or X unless it 
is the final location being loaded . 



assume that AC is thej5anie_afjgMhgJ 



j 



EXAMPLES. This pair of instructions loads the accumulators from memory 
locations 2000-20 17. 



HRLZI 
BLT 



17,2000 
17,17 



;Put 2000 000000 in AC 17 



But to transfer the block in the opposite direction requires that one accumu- 
lator first be made available to the BLT: 



MOVEM 17,2017 
MOVEI 17,2000 
BLT 17,2016 



;Move AC 17 to 2017 in memory 
;Move the number 2000 to AC 17 



If at the time the accumulators were loaded the program had placed in loca- 
tion 2017 the control word necessary for storing them back in the same 
block (2000), the three instructions above could be replaced by 



EXCH 
BLT 



17,2017 
17,2016 



Move Instructions 

Each of these instructions moves a single word, which may be changed in the 
process (eg its two halves may be swapped). There are four instructions, 



2.2 



FULL WORD DATA TRANSMISSION 



2-11 



each with four modes that determine the source and destination of the word 
moved. 



Mode 

Basic 

Immediate 
Memory 
Self 



Suffix 

I 

M 
S 



Source 

E 

The word 0, 

AC 

E 



Destination 

AC 
AC 

E 

E, but also AC 
if A is nonzero 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /is in memory 
mode, .20 (.09) MS in self 
mode. 

When E addresses a fast 
memory location, a move in- 
struction takes .34 MS less in 
basic mode, .46 (.35) MS less 
in memory mode, .54 (.43) MS 
less in self mode. 



MOVE 



Move 



200 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



1718 



35 



Move one word from the source to the destination specified by M. The 
source is unaffected, the original contents of the destination are lost. 



MOVE Move 

MOVEI Move Immediate 

MOVEM Move to Memory 

MOVES Move to Self 



200 2.21 (2.43) jus 

201 1.36 (1.47) us 

202 2.47 (2.58) MS 

203 2.76 (2.87) MS 



MOVEI loads the word 0,E 
into AC and is thus equiva- 
lent to HRRZI. If A is zero, 
MOVES is a no-op; otherwise 
it is equivalent to MOVE. 



MOVS 



Move Swapped 



204 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Interchange the left and right halves of the word from the source specified 
by M and move it to the specified destination. The source is unaffected, the 
original contents of the destination are lost. 



MOVS Move Swapped 

MOVSI Move Swapped Immediate 

MOVSM Move Swapped to Memory 

MOVSS Move Swapped to Self 



204 2.21 (2.43) /is 

205 1.36 (1.47) MS 

206 2.47 (2.58) MS 

207 2.76 (2.87) MS 



Swapping halves in immediate 
mode loads the word ",0 into 
AC. MOVSI is thus equivalent 
to HRLZI. 



MOVN 



Move Negative 



2 10 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Negate the word from the source specified by M and move it to the specified 
destination. If the source word is fixed point -2 35 (400000 000000) set the 



MAY 1968 



2-12 



CENTRAL PROCESSOR 



2.: 



MOVNI loads AC with the 
negative of the word 0,E and 
can set no flags. 



Overflow and Carry 1 flags. (Negating the equivalent floating point -1 X 2 127 
sets the flags, but this is not a normalized number.) If the source word is 
zero, set Carry and Carry 1. The source is unaffected, the original contents 
of the destination are lost. 



MOVN Move Negative 

MOVNI Move Negative Immediate 

MOVNM Move Negative to Memory 

MOVNS Move Negative to Self 



210 2.39 (2.61) MS 

211 1.54(1.65)MS 

212 2.65 (2.76) MS 

213 2.94 (3.05) MS 



The word 0," is equivalent 
to its magnitude, so MOVMI 
is equivalent to MOVEI. 



MOVM 



Move Magnitude 



2 14 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Take the magnitude of the word contained in the source specified by M and 
move it to the specified destination. If the source word is fixed point 2 3S 
(400000 000000) set the Overflow and Carry 1 flags. (Negating the equiva- 
lent floating point -1 X 2 127 sets the flags, but this is not a normalized num- 
ber.) The source is unaffected, the original contents of the destination are 
lost. 



MOVM Move Magnitude 

MOVMI Move Magnitude Immediate 

MOVMM Move Magnitude to Memory 

MOVMS Move Magnitude to Self 



214 2. 39 (2.61) MS 

215 1.54 (1.65) MS 

216 2.65 (2.76) MS 

217 2.94 (3.05) MS 



An example at the end of the preceding section demonstrates the use of a 
pair of immediate-mode half word transfers to load an address and a control 
count into an accumulator. The same result can be attained by a single move 
instruction. This saves time but still requires two locations. Eg if the num- 
ber 200 001400 is stored in location M, the instruction 

MOVE AC,M 

loads 200 into AC left and 1400 into AC right. If the same word, or its nega- 
tive, or with its halves swapped, must be loaded on several occasions, then 
both time and space can be saved as each transfer requires only a single move 
instruction that references M. 



Pushdown List 

These two instructions insert and remove full words in a pushdown list. The 
address of the top item in the list is kept in the right half of a pointer in AC, 
and the program can keep a control count in the left half. There are also 



MAY 1968 



2.2 



FULL WORD DATA TRANSMISSION 



2-13 



two subroutine-calling instructions that utilize a pushdown list of jump ad- 
dresses [ 2.9] . 



PUSH 



Push Down 



3.85 (4.07) 



261 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC to increment both halves by one, then move the con- 
tents of location E to the location^ npw^d^res^edby_AC_rjght) If the addi- 
tion causes the count in AC left toreach zero, s?t the Pushdown Overflow 
flag. The contents of E are unaffected, the original contents of the location 
added to the list are lost. 




POP 



Pop Up 



3.93 (4. 15) 



262 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Move the contents of the location addressed by AC right to location E, then 
subtract 1 00000 1 8 from AC to decrement both halves by one. If the sub- 
traction causes the count in AC left to reach - 1 , set the Pushdown Overflow 
flag. The original contents of E are lost. 

Because of the order in which the operands are stored, the instruction 
POP AC, AC would load the contents of the location addressed by AC right 
into AC on top of the pushdown count, destroying it. 



Keeping instructions and the 
pushdown list in different 
memories saves .47 (.36) MS. 

When the word added to 
the list is from fast memory, 
PUSH takes .34 MS less than 
the time given. 



When the word taken from 
the list is placed in fast mem- 
ory, POP takes .46 (.35) MS 
less than the time given. 



The incrementing and decrementing of both halves of AC simultaneously 
is effected by adding and subtracting 1 00000 1 8 . Hence a count of -2 in AC 
left is increased to zero if 2 18 - 1 is incremented in AC right, and conversely, 
1 in AC left is decreased to - 1 if zero is decremented in AC right. 

A pushdown list is simply a set of consecutive memory locations from 
which words are read in the order opposite that in which they are written. 
In more general terms, it is any list in which the only item that can be re- 
moved at any given time is the last item in the list. This is usually referred 
to as "first in, last out" or "last in, first out". Suppose locations a, b, c, ... 
are set aside for a pushdown list. We can deposit data in a, b, c, d, then read 
d, then write in d and e, then read e, d, c, etc. -r 

" Note that by using the Pushdown Overflow flag and a control count in AC 
left, the programmer can set a limit to the size of the list by starting the 
count negative, or he can prevent the program from extracting more words 
than there are in the list by starting the count at zero, but he cannot do both 
at once. 



2-14 CENTRAL PROCESSOR 2.2 

Pushdown storage is very convenient for a program that can use data 
stored in this manner as the pointer is initialized only once and only one 
accumulator is required for the most complex pushdown operations. To ini- 
tialize a pointer P for a list to be kept in a block of memory beginning at 
BLIST and to contain at most N items, the following suffices. 

MOVSI P,-/V 
HRRI P,BLIST-1 

Of course the programmer must define BLIST elsewhere and set aside loca- 
tions BLIST to BLIST + N - \. Using MACRO to full advantage one could 
instead give 

MOVE P,[IOWD 7V,BLIST] 
where the pseudoinstruction 

IOWD J,K 

is replaced by a word containing -J in the left half and K - 1 in the right. 
Elsewhere there would appear 

BLIST: BLOCK TV 

which defines BLIST as the current contents of the location counter and sets 
aside the TV locations beginning at that point. 

In the POP- 10 the pushdown list is kept in a random access core mem- 
ory, so the restrictions on order of entry and removal of items actually apply 
only to the standard addressing by the pointer in pushdown instructions - 
other addressing methods can reference any item at any time. The most 
convenient way to do this is to use the right half of the pointer as an index 
register. To move the last entry to accumulator AC we need simply give 

MOVE AC,(P) 

Of course this does not shorten the list the word moved remains the last 
item in it. 

One usually regards an index register as supplying an additive factor for a 
basic address contained in an instruction word, but the index register can 
supply the basic address and the instruction the additive factor. Thus we can 
retrieve the next to last item by giving 

MOVE AC,-1(P) 
and so forth. Similarly 

PUSH P,-3(P) 
adds the third to last item to the end of the list; 

POP P,-2(P) 

removes the last item and inserts it in place of the next to last item in the 
shortened list. 



2.3 BYTE MANIPULATION 2-15 

2.3 BYTE MANIPULATION 

This set of five instructions allows the programmer to pack or unpack bytes 
of any length anywhere within a word. Movement of a byte is always 
between AC and a memory location: a deposit instruction takes a byte from 
the right end of AC and inserts it at any desired position in the memory 
location; a load instruction takes a byte from any position in the memory 
location and places it right-justified in AC. 

The byte manipulation instructions have the standard memory reference 
format, but the effective address E is used to retrieve a pointer, which is used 
in turn to locate the byte or the place that will receive it. The pointer has 
the format 



p 


s 




I 


X 


Y 



56 11 12 13 14 17 18 35 

where S is the size of the byte as a number of bits, and P is its position as the 
number of bits remaining at the right of the byte in the word (eg if P is 3 the 
rightmost bit of the byte is bit 32 of the word). The rest of the pointer is 
interpreted in the same way as in an instruction: /, X and Y are used to cal- 
culate the address of the location that is the source or destination of the 
byte. Thus the pointer aims at a word whose format is 



P BITS 



35-P-S+l 3S-P 35-.P + I 35 

where the shaded area is the byte. 

To facilitate processing a series of bytes, several of the byte instructions 
increment the pointer, ie modify it so that it points to the next byte position 
in a set of memory locations. Bytes are processed from left to right in a 
word, so incrementing merely replaces the current value of P by P - S, unless 
there is insufficient space in the present location for another byte of the 
specified size (P - S < 0). In this case Y is increased by one to point to the 
next consecutive location, and P is set to 36 S to point to the first byte at 
the left in the new location. 

CAUTION 

Do not allow Y to reach maximum value. The whole pointer is incre- 
mented, so if Y is 2 18 - 1 it becomes zero and X is also incremented. 
The address calculation for the pointer uses the original X, but if a pri- 
ority interrupt should occur before the calculation is complete, the in- 
cremented X is used when the instruction is repeated. 

Among these five instructions one simply increments the pointer, the 
others load or deposit a byte with or without incrementing. Brackets 
enclose the additional time required when incrementing overflows the word 
boundary. 



2-16 



CENTRAL PROCESSOR 



2.3 



Keeping the pointer in fast 
memory saves .34 jus. Taking 
bytes from a fast memory 
location saves another .34 /us. 



LDB 



Load Byte 



4.02(4.35) + A5(P + S) [+.26] /us 



135 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Retrieve a byte of S bits from the location and position specified by the 
pointer contained in location E, load it into the right end of AC, and clear 
the remaining AC bits. The location containing the byte is unaffected, the 
original contents of AC are lost. 



Keeping the pointer in fast 
memory saves .34 jus. Keeping 
instructions and the packing 
area in different memories 
saves .20 (.09) /us. Packing 
bytes in fast memory saves 
.54 (.43) /us. 



DPB 



Deposit Byte 



4.87(5.20) + .15CP 



89 



12 13 14 



17 18 



[+.26] jus 



137 


A 


I 


X 


Y 



35 



Deposit the right S bits of AC into the location and position specified by the 
pointer contained in location E. The original contents of the bits that receive 
the byte are lost, AC and the remaining bits of the deposit location are 
unaffected. 



Keeping the pointer in fast 
memory saves .54 (.43) /us; 
keeping it in a different mem- 
ory from the instruction saves 
.20 (.09) /us 

The A portion of this instruc- 
tion is ignored. 



IBP 



Increment Byte Pointer 



2.87(2.98) [+.26] jus 



133 


A 


I 


X 


Y 



89 121314 1718 

Increment the byte pointer in location E as explained above. 



35 



Keeping the pointer in fast 
memory saves .34 /us. Taking 
bytes from a fast memory 
location saves another .34 /us. 



ILDB 



Increment Pointer and Load Byte 



4.24 (4.57) 



89 



12 13 14 



17 18 



[+.26] /us 



134 


A 


1 


X 


Y 



35 



Increment the byte pointer in location E as explained above. Then retrieve a 
byte of S bits from the location and position specified by the newly incre- 
mented pointer, load it into the right end of AC, and clear the remaining AC 
bits. The location containing the byte is unaffected, the original contents of 
AC are lost. 



Keeping the pointer in fast 
memory saves .34 /us. Keeping 
instructions and the packing 
area in different memories 
saves .20 (.09) /us. Packing 
bytes in fast memory saves 
.54 (.43) jus. 



IDPB Increment Pointer and Deposit Byte 

5.29(5.51) + A5(P + S) [+.26] /us 



136 


A 


I 


X 


Y 



89 12 13 14 17 18 35 

Increment the byte pointer in location E as explained above. Then deposit 



2.4 



LOGIC 



2-17 



the right S bits of AC into the location and position specified by the newly 
incremented pointer. The original contents of the bits that receive the byte 
are lost, AC and the remaining bits of the deposit location are unaffected. 



Note that in the pair of instructions that both increment the pointer and 
process a byte, it is the modified pointer that determines the byte location 
and position. Hence to unpack bytes from a block of memory, the program 
should set up the pointer to point to a byte just before the first desired, and 
then load them with a loop containing an ILDB. If the first byte is at the 
left end of a word, this is most easily done by initializing the pointer with a 
P of 36 (44 8 ). Incrementing then replaces the 36 with 36 S to point to the 
first byte. At any time that the program might inspect the pointer during 
execution of a series of ILDBs or IDPBs, it points to the last byte processed 
(this may not be true when the pointer is tested from an interrupt routine 
[2.13]). 

Special Considerations. If S is greater than P and also greater than 36, 
incrementing produces a new P equal to lOO-S rather than 36-5. For 
S> 36 the byte is at most the entire word; for /> 36 no byte is processed 
(loading merely clears AC). If both P and S are less than 36 but P + S > 36, 
a byte of size 36 - P is loaded from position P. or the'right 36 - P bits of the 
byte are deposited in position P. 



2.4 LOGIC 



For logical operations the PDF- 10 has instructions for shifting and rotating 
as well as for performing the complete set of sixteen Boolean functions of 
two variables (including those in which the result depends on only one or 
neither variable). The Boolean functions operate bitwise on full words, so 
each instruction actually performs thirty-six logical operations simultane- 
ously. Thus in the AND function of two words, each bit of the result is the 
AND of the corresponding bits of the operands. The table on page 2-23 lists 
the bit configurations that result from the various operand configurations for 
all instructions. 

Each Boolean instruction has four modes that determine the source of the 
non-AC operand, if any, and the destination of the result. 



Mode 

Basic 

Immediate 
Memory 
Both 



Suffix 

I 

M 
B 



Source of non- 
AC operand 



The word 0, 
E 
E 



Destination 
of result 

AC 
AC 

E 
AC and E 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) p.s in memory 
and both modes in the first 
four of these instructions 
(those that have no operand 
or only an AC operand), .20 
(.09) /us in memory and both 
modes in the remaining 
twelve (those that have a 
memory or immediate op- 
erand). 



2-18 



CENTRAL PROCESSOR 



2.4 



A Boolean instruction in 
which E addresses a fast 
memory location takes .46 
(.35) M S less in memory or 
both mode if it has no oper- 
and or only an AC operand. 
If it has a memory operand, 
it takes .34 /us less in basic 
mode, .54 (.43) MS less in 
memory or both mode. 



SETZ and SETZI are equiva- 
lent (both merely clear AC). 
MACRO also recognizes 
CLEAR, CLEARI, CLEARM 
and CLEARS as equivalent to 
the set-to-zeros mnemonics. 



For an instruction without an operand (one that merely clears a location or 
sets it to all Is) the modes differ only in the destination of the result, so 
basic and immediate modes are equivalent. The same is true also of an 
instruction that uses only an AC operand. When specified by the mode, the 
result goes to the accumulator addressed by A, even when there is no AC 
operand. 



SETZ 



Set to Zeros 



400 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to all Os. 

SETZ Set to Zeros 400 1.36 (1.47) MS 

SETZI Set to Zeros Immediate 401 1.36 (1.47) MS 

SETZM Set to Zeros Memory 402 2. 33 (2.44) MS 

SETZB Set to Zeros Both 403 2.33 (2.44) MS 



SETO and SETOI are equiva- 
lent. 



SETO 



Set to Ones 



474 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to all 1 s. 

SETO Set to Ones 474 1.36 (1.47) MS 

SETOI Set to Ones Immediate 475 1.36 (1.47) MS 

SETOM Set to Ones Memory 476 2.33 (2.44) MS 

SETOB Set to Ones Both 477 2.33 (2.44) MS 



SETA and SETAI are no-ops. 
SETAM and SETAB are both 
equivalent to MOVEM (all 
move AC to location E). 



SETA 



Set to AC 



424 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Make the contents of the destination specified by M equal to AC. 

SETA Set to AC 424 1.50 (1.61) MS 

SETAI Set to AC Immediate 425 1.50 (1.61) MS 

SETAM Set to AC Memory 426 2.47 (2.58) MS 

SETAB Set to AC Both 427 2.47 (2.58) MS 



2.4 
SETCA 



LOGIC 



Set to Complement of AC 



450 


M 


A 


I 


X 


Y 



6789 12 13 14 17 18 



35 



Change the contents of the destination specified by M to the complement of 
AC. 



SETCA Set to Complement of AC 

SETCAI Set to Complement of AC Immediate 

SETCAM Set to Complement of AC Memory 

SETCAB Set to Complement of AC Both 



450 
1.50 (1.61) jus 

451 
1.50 (1.61) MS 

452 
2.47 (2.58) MS 

453 
2.47 (2.58) MS 



2-19 



SETCA and SETCAI are 
equivalent (both complement 
AC). 



SETM 



4 14 



Set to Memory 



M 



X 



67 89 



12 13 14 



17 18 



35 



Make the contents of the destination specified by M equal to the specified 
operand. 

SETM Set to Memory 414 2.21 (2.43) MS 

SETM I Set to Memory Immediate 415 1.36 (1.47) MS 

SETMM Set to Memory Memory 416 2.76 (2.87) MS 

SETMB Set to Memory Both 417 2.76 (2.87) MS 



SETM and SETMB are equiv- 
alent to MOVE. SETMI 
moves the word 0," to AC 
and is thus equivalent to 
MOVEI. SETMM is a no-op 
that references memory. 



SETCM 



Set to Complement of Memory 



460 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the complement of 
the specified operand. 



SETCM Set to Complement of Memory 

SETCM I Set to Complement of Memory Immediate 

SETCMM Set to Complement of Memory Memory 

SETCMB Set to Complement of Memory Both 



460 
2.21 (2.43) MS 

461 
1.36 (1.47) MS 

462 
2.76 (2.87) MS 

463 
2.76 (2.87) MS 



SETCM I moves the comple- 
ment of the word Q,E to AC. 
SETCMM complements loca- 
tion E. 



2-20 



CENTRAL PROCESSOR 



2.4 



AND 



And with AC 



404 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the AND function of 
the specified operand and AC. 

AND And 404 2.35 (2.57) /us 

ANDI And Immediate 405 1.50 (1.61) MS 

ANDM And to Memory 406 2. 90 (3. 01) MS 

ANDB And to Both 407 2.90 (3.01) MS 



ANDCA And with Complement of AC 



410 



M 



X 



Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the AND function of 
the specified operand and the complement of AC. 

410 
2.70 (2.92) MS 

411 
1.85 (1.96) MS 

412 
3. 52 (3.63) MS 

AIM D CAB And with Complement of AC to Both 4 1 3 

3.52 (3. 63) MS 



AN D C A And with Complement of AC 

ANDCAI And with Complement of AC Immediate 

ANDCAM And with Complement of AC to Memory 



AIMDCM And Complement of Memory with AC 



420 


M 


A 


I 


X 


Y 



67 89 



12 13 14 17 18 



35 



Change the contents of the destination specified by M to the AND function of 
the complement of the specified operand and AC. 



ANDCM And Complement of Memory 

ANDCMI And Complement of Memory Immediate 

ANDCMM And Complement of Memory to Memory 

ANDCMB And Complement of Memory to Both 



420 
2.35 (2.57) MS 

421 
1.50(1.61)MS 

422 
2.90 (3.01) MS 

423 
2.90 (3.01) MS 



2.4 
ANDCB 



LOGIC 



And Complements of Both 



440 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the AND function of 
the complements of both the specified operand and AC. The result is the 
NOR function of the operands. 



ANDCB And Complements of Both 

AIMDCBI And Complements of Both Immediate 

AIMDCBM And Complements of Both to Memory 

ANDCBB And Complements of Both to Both 



440 
2.70 (2.92) MS 

441 
1.85 (1.96) MS 

442 
3.52 (3.63) MS 

443 
3.52 (3.63) MS 



2-21 



IOR 



434 



Inclusive Or with AC 



M 



X 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the inclusive OR 
function of the specified operand and AC. 

IOR Inclusive Or 434 2.35 (2.57) MS 

IORI Inclusive Or Immediate 435 1.50 (1.61) /us 

IORM Inclusive Or to Memory 436 2.90 (3. 01) MS 

IORB Inclusive Or to Both 437 2.90 (3.01) MS 



MACRO also recognizes OR, 
ORI, ORM and ORB as equiv- 
alent to the inclusive OR mne- 
monics. 



ORCA 



Inclusive Or with Complement of AC 



454 


M 


A 


I 


X 


Y 



67 89 121314 1718 



35 



Change the contents of the destination specified by M to the inclusive OR 
function of the specified operand and the complement of AC. 



ORCA Or with Complement of AC 

ORCAI Or with Complement of AC Immediate 



454 

2.70 (2.92) MS 
455 
1.85 (1.96) MS 

ORCAM Or with Complement of AC to Memory 456 

3.52 (3.63) MS 

R CAB Or with Complement of AC to Both 457 

3.52 (3.63) MS 



2-22 



CENTRAL PROCESSOR 



2.4 



ORCM 



Inclusive Or Complement of Memory with AC 



464 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the inclusive OR 
function of the complement of the specified operand and AC. 

ORCM Or Complement of Memory 464 

2.35 (2.57) MS 
ORCMI Or Complement of Memory Immediate 465 

1 .50 (1.61) f 
ORCMM Or Complement of Memory to Memory 466 

2.90 (3.01) MS 
ORCMB Or Complement of Memory to Both 467 

2.90 (3.01) MS 



ORCB Inclusive Or Complements of Both 


470 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the inclusive OR 
function of the complements of both the specified operand and AC. The 
result is the NAND function of the operands. 

ORCB Or Complements of Both 



ORCBI Or Complements of Both Immediate 

ORCBM Or Complements of Both to Memory 
ORCBB Or Complements of Both to Both 



470 
2.70 (2.92) MS 

471 
1.85 (1.96) MS 

472 
3. 52 (3.63) MS 

473 
3.52 (3.63) MS 



XOR 



Exclusive Or with AC 



430 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the exclusive OR 
function of the specified operand and AC. 



XOR Exclusive Or 

XORI Exclusive Or Immediate 

XORM Exclusive Or to Memory 

XO R B Exclusive Or to Both 



430 2.35 (2.57) MS 

431 1.50(1. 61)MS 

432 2.90 (3.01) MS 

433 2.90 (3.01) MS 



The original contents of the destination can be recovered except in XORB, 
where both operands are replaced by the result. In the other three modes 
the replaced operand is restored by repeating the instruction in the same 
mode, ie by taking the exclusive OR of the remaining operand and the result. 



2.4 LOGIC 2-23 

EQV Equivalence with AC 



444 



M 



X 



67 89 121314 1718 35 

Change the contents of the destination specified by M to the complement of 
the exclusive OR function of the specified operand and AC (the result has Is 
wherever the corresponding bits of the operands are the same). 

EQV Equivalence 444 2.35 (2.57) jus 

EQVI Equivalence Immediate 445 1.50 (1.61) jus 

EQVM Equivalence to Memory 446 2.90 (3.01) /us 

EQVB Equivalence to Both 447 2.90 (3.01) jus 

The original contents of the destination can be recovered except in EQVB, 
where both operands are replaced by the result. In the other three modes 
the replaced operand is restored by repeating the instruction in the same 
mode, ie by taking the equivalence function of the remaining operand and 
the result. 



For the four possible bit configurations of the two operands, the above 
sixteen instructions produce the following results. In each case the result as 
listed is equal to bits 3-6 of the instruction word. 



AC 

Mode Specified Operand 






1 






1 


1 
1 


SETZ 














AND 











1 


ANDCA 








1 





SETM 








1 


1 


ANDCM 





1 








SETA 





1 





1 


XOR 





1 


1 





IOR 





1 


1 


1 


ANDCB 


1 











EQV 


1 








1 


SETCA 


1 





1 





ORCA 


1 





1 


1 


SETCM 


1 


1 








ORCM 


1 


1 





1 


ORCB 


1 


1 


1 





SETO 


1 


1 


1 


1 



2-24 



CENTRAL PROCESSOR 



2.4 



Shift and Rotate 



The remaining logical instructions shift or rotate right or left the contents of 
AC or the contents of two accumulators, A and A + l (mod 20 8 ), concat- 
enated into a 72-bit register with A on the left. The illustration below 
shows the movement of information these instructions produce in the accu- 



LSH 











A 










35 



LSHC 






















A 




A + 1 




f) 

















35 



35 



ROT 









A 










3 35 



ROTC 

























A 




A + 1 
















3 35 




3 35 





ASH 



A 



35 



ASHC 

































A 










4+1* 






















































A 




4 + 1 '0 

















35 1 



35 



ACCUMULATOR BIT FLOW IN SHIFT AND ROTATE INSTRUCTIONS 



2.4 



LOGIC 



mulators. In a (logical) shift the contents of a register are moved bit-to-bit 
with Os brought in at the end being vacated; information shifted out at the 
other end is lost. [For a discussion of arithmetic shifting see 2.5J In- 
rotation the rnrrtnrb nrp mnvi il i ji Hi .illy 'lui'li thnt intnrmntinn rotated out 
in at the other. 



The number of places moved is specified by the result of the effective 
address calculation taken as a signed number (in twos complement notation) 
modulo 2 8 in magnitude. In other words the effective shift E is the number 
composed of bit 18 (which is the sign) and bits 28-35 of the calculation 
result. Hence the programmer may specify the shift directly in the instruc- 
tion (perhaps indexed) or give an indirect address to be used in calculating 
the shift. A positive E produces motion to the left, a negative E to the right; 
maximum movement is 255 places. ____ 



2-25 






LSH Logical Shift Left: 
Right: 


1.62 
1.46 


(1 
(1 


.73) + .! 
.57) + .! 


5|| MS 
5[E\ MS 


242 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Shift AC the number of places specified by E. If E is positive, shift left 
bringing Os into bit 35; data shifted out of bit is lost. If E is negative, shift 
right bringing Os into bit 0; data shifted out of bit 35 is lost. 



LSHC Logical Shift Combined Left: 
Right: 


2.00(2.11) + .15||/zs 
1.84(1.95) + .15||MS 


246 A i 


' X 


Y 



89 



12 13 14 



17 18 



35 



Concatenate accumulators A and A + l with A on the left, and shift the 
72-bit combination the number of places specified by E. If E is positive, 
shift left bringing Os into bit 71 (bit 35 of AC ,4 + 1); bit 36 is shifted into bit 
35 ; data shifted out of bit is lost. If E is negative, shift right bringing Os 
into bit 0; bit 35 is shifted into bit 36; data shifted out of bit 71 is lost. 



ROT Rotate Left: 
Right: 


1.62 
1.46 


(1 
(1 


.73) + .1 
.57) + .! 


5\E\ MS 
5 1.1 MS 


241 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Rotate AC the number of places specified by E. If E is positive, rotate left; 
bit is rotated into bit 35. If E is negative, rotate right; bit 35 is rotated 
into bit 0. 



2-26 



CENTRAL PROCESSOR 



i2.5 



ROTC 



Rotate Combined 



Left: 2.00(2.11) + .15||/us 
Right: 1.84(1.95)"+ .15|| jus 



245 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Concatenate accumulators A and A + l with A on the left, and rotate the 
72-bit combination the number of places specified by E. If E is positive, 
rotate left; bit is rotated into bit 71 (bit 35 of ACM + 1) and bit 36 into bit 
35. If E is negative, rotate right; bit 35 is rotated into bit 36 and bit 7 1 into 
bitO. 



2.5 FIXED POINT ARITHMETIC 



Overflow is determined di- 
rectly from the carries, not 
from the carry flags, as their 
states may reflect events in 
previous instructions. 



For fixed point arithmetic the PDF- 10 has instructions for arithmetic shift- 
ing (which is essentially multiplication by a power of 2) as well as for per- 
forming addition, subtraction, multiplication and division of numbers in 
fixed point format [1.1]. In such numbers the position of the binary point 
is arbitrary (the programmer may adopt any point convention). The add and 
subtract instructions involve only single length numbers, whereas multiply 
supplies a double length product, and divide uses a double length dividend. 
The high and low order words respectively of a double length fixed point 
number are in accumulators A and A + l (mod 20 8 ), where the magnitude is 
the 70-bit string in bits 1-35 of the two words and the signs of the two are 
identical. There are also integer multiply and divide instructions that involve 
only single length numbers and are especially suited for handling smaller 
integers, particularly those of eighteen bits or less such as addresses (of 
course they can be used for small fractions as well provided the programmer 
keeps track of the binary point). For convenience in the following, all oper- 
ands are assumed to be integers (binary point at the right). 

The processor has four flags, Overflow, Carry 0, Carry 1 and No Divide, 
that indicate when the magnitude of a number is or would be larger than can 
be accommodated. Carry and Carry 1 actually detect carries out of bits 
and 1 in certain instructions that employ fixed point arithmetic operations: 
the add and subtract instructions treated here, the move instructions that 
produce the negative or magnitude of the word moved [2.2], and the 
arithmetic test instructions that increment or decrement the test word 
[ 2.7] . In these instructions an incorrect result is indicated and the Over- 
flow flag set - if the carries are different, ie if there is a carry into the sign 
but not out of it, or vice versa. The Overflow flag is also set by No Divide 
being set, which means the processor has failed to perform a division because 
the magnitude of the dividend is greater than or equal to that of the divisor, 
or in integer divide, simply that the divisor is zero. In other overflow cases 
only Overflow itself is set: these include too large a product in multiplica- 
tion, and loss of significant bits in left arithmetic shifting. 

These flags can be read and controlled by certain program control instruc- 
tions [ 2.9] , and Overflow is available as a processor condition (via in-out 



2.5 



FIXED POINT ARITHMETIC 



2-27 



instructions [2.14]) that can request a priority interrupt if enabled. The 
conditions detected can only set the flags and the hardware does not clear 
them, so the program must clear them before an instruction if they are to 
give meaningful information about the instruction afterward. However, the 
program can check the flags following a series of instructions to determine 
whether the entire series was free of the types of error detected. 

All but the shift instructions have four modes that determine the source 
of the non-AC operand and the destination of the result. 



Mode 

Basic 

Immediate 
Memory 
Both 



Suffix 

I 

M 

B 



Source of non- 
AC operand 


Destination 
of result 


E 


AC 


The word 0,E 


AC 


E 


E 


E 


AC and E 



Besides indicating error types, 
the carry flags facilitate per- 
forming multiple precision 
arithmetic. 



ADD 



Add 



270 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Add the operand specified by M to AC and place the result in the specified 
destination. If the sum is > 2 35 set Overflow and Carry 1 ; the result stored 
has a minus sign but a magnitude in positive form equal to the sum less 2 3S . 
If the sum is < -2 3S set Overflow and Carry 0; the result stored has a plus 
sign but a magnitude in negative form equal to the sum plus 2 35 . Set both 
carry flags if both summands are negative, or their signs differ and their mag- 
nitudes are equal or the positive one is the greater in magnitude. 



ADD Add 

ADD I Add Immediate 

ADDM Add to Memory 

ADDB Add to Both 

SUB Subtract 



270 2.53 (2.75) MS 

271 1.68 (1.79) jus 

272 3.08 (3. 19) MS 

273 3.08 (3. 19) MS 



274 


M 


,1 


/ 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Subtract the operand specified by M from AC and place the result in the 
specified destination. If the difference is > 2 35 set Overflow and Carry 1 ; 
the result stored has a minus sign but a magnitude in positive form equal to 
the difference less 2 3S . If the difference is < -2 35 set Overflow and Carry 0; 
the result stored has a plus sign but a magnitude in negative form equal to 
the difference plus 2 3S . Set both carry flags if the signs of the operands are 
the same and AC is the greater or the two are equal, or the signs of the 
operands differ and AC is negative. 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) /us in ADDM 
and ADDB. 

When E addresses a fast 
memory location, ADD takes 
.34 jus less than the time 
given, ADDM and ADDB take 
.54 (.43) jus less. 



MAY 1968 



2-28 



CENTRAL PROCESSOR 



2.5 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) MS in SUBM 
and SUBB. 

When E addresses a fast 
memory location, SUB takes 
.34 us less than the time 
given, SUBM and SUBB take 
.54 (.43) /us less. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) jus in MULM, 
.31 (.20) MS in MULB. 

When E addresses a fast 
memory location, MUL takes 
.34 /us less than the time 
given, MULM takes .80 (.69) 
MS less, and MULB takes .64 
(.53) MS less. 



SUB Subtract 

SUBI Subtract Immediate 

SUBM Subtract to Memory 

SUBB Subtract to Both 



MUL Multiply 



274 2. 53 (2. 75) MS 

275 1.68 (1.79) MS 

276 3.08 (3. 19) MS 

277 3.08 (3. 19) MS 



224 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Multiply AC by the operand specified by M, and place the high order word 
of the double length result in the specified destination. If M specifies AC as 
a destination, place the low order word in accumulator A + l. If both oper- 
ands are -2 35 set Overflow; the double length result stored is -2 70 . 



MUL Multiply 

MULI Multiply Immediate 

MULM Multiply to Memory 

MULB Multiply to Both 



224 10.60 (10.82) MS 

225 8. 58 (8.69) MS 

226 11.41 (11. 63) MS 

227 11.41 (11.63) /us 



Timing. The times given above are average. The algorithm modifies the 
running sum of partial products at each 1-0 or 0-1 transition scanning from 
one bit to the next in the multiplier, which is the operand specified by the 
mode; in other words the number of operations equals the number of pairs 
of adjacent bits that differ in the multiplier including the sign bit and taking 
the bit at the right of the LSB as (an LSB of 1 is regarded as a transition). 
Minimum times with a zero multiplier are 



MUL 
MULI 
MULM 
MULB 



8. 26 (8.48) MS 
7.41 (7. 52) MS 
9.07 (9. 29) MS 
9.07 (9.29) MS 



These must be increased by .13 MS for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



IMUL 



Integer Multiply 



220 



M 



X 



67 89 



12 13 14 



17 18 



35 



Multiply AC by the operand specified by M, and place the sign and the 35 
low order magnitude bits of the product in the specified destination. Set 
Overflow if the product is > 2 35 or < -2 35 (ie if the high order word of the 
double length product is not null); the high order word is lost. 



2.5 



FIXEDu POINT ARITHMETIC 



2-29 



IMUL Integer Multiply 

IMULI Integer Multiply Immediate 

IMULM Integer Multiply to Memory 

IMULB Integer Multiply to Both 



220 9.59 (9.81) jus 

221 8.09 (8.20) jus 

222 10.56 (10.78) MS 

223 10.56 (10.78) /is 



Timing. The times given above are average. Refer to the description of 
MUL for the timing effects of the multiplication algorithm. Minimum times 
with a zero multiplier are 



IMUL 
IMULI 
IMULM 
IMULB 



8.42 (8.64) MS 
7.57 (7.68) MS 
9.39 (9.61) MS 
9.39 (9.61) MS 



These must be increased by .13 MS for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) jus in IMULM 
and IMULB. 

When E addresses a fast 
memory location, IMUL 
takes .34 jus less than the time 
given, IMULM and IMULB 
take .80 (.69) jus less. 



DIV 



Divide 



234 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



If the magnitude of the number in AC is greater than or equal to that of the 
operand specified by M, set Overflow and No Divide, and go immediately to 
the next instruction without affecting the original AC or memory operand in 
any way. Otherwise divide the double length number contained in accumula- 
tors A and A + l by the specified operand, calculating a quotient of 35 
magnitude bits including leading zeros. Place the unrounded quotient in the 
specified destination. If M specifies AC as a destination, place the remainder, 
with the same sign as the dividend, in accumulator A + 1 . 



DIV Divide 

DIVI Divide Immediate 

DIVM Divide to Memory 

DIVB Divide to Both 



I DIV Integer Divide 



234 
235 
236 
237 



16.2 (16.4) MS 
15.4(15. 5) MS 
17.1 (17.3) MS 
17.1 (17.3) MS 



230 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



If the operand specified by M is zero, set Overflow and No Divide, and go 
immediately to the next instruction without affecting the original AC or 
memory operand in any way. Otherwise divide AC by the specified operand, 
calculating a quotient of 35 magnitude bits including leading zeros. Place 



Keeping instructions and op- 
erands in different memories 
saves .5 (.4) MS in DIVM, .3 
(.2) /us in DIVB. 

When E addresses a fast 
memory location, DIV takes 
.3 MS less than the time given, 
DIVM takes .8 (.7) us less, 
and DIVB takes .6 (.5) MS 
less. 

If the division is not per- 
formed, only 2.5-3 MS are 
required. 



2-30 



CENTRAL PROCESSOR 



2.5 



the unrounded quotient in the specified destination. If M specifies AC as the 
destination, place the remainder, with the same sign as the dividend, in 
accumulator A + 1 . 



Keeping instructions and op- 
erands in different memories 
saves .5 (.4) /ts in IDIVM, .3 
(.2) us in IDIVB. 

When E addresses a fast 
memory location, IDIV takes 
.3 MS less than the time given, 
IDIVM takes .8 (.7) MS less, 
and IDIVB takes .6 (.5) /is 
less. 

If the division is not per- 
formed, only 3-3.5 /is are 
required. 



IDIV Integer Divide 

I D I V I Integer Divide Immediate 

IDIVM Integer Divide to Memory 

IDIVB Integer Divide to Both 



230 16.5 (16.7) /is 

231 15.7 (15. 8) MS 

232 17.4 (17.6) MS 

233 17.4 (17.6) MS 



EXAMPLE. The integer multiply and divide instructions are very useful for 
computations on addresses or character codes, or performing any integral 
operations in which the result is small enough to be accommodated in a 
single register. 

As an example suppose we wish to determine the parity of the 8-bit char- 
acter abcdefgh, where the letters represent the bits of the character. Assum- 
ing the character is right-justified in AC, we first duplicate it twice to the left 
producing 

abc def gha bed efg hob cde fgh 

where the bits (in positions 12-35) are grouped corresponding to the octal 
digits in the word. Anding this with 

001 001 001 001 001 001 001 001 

retains only the least significant bit in each 3-bit set, so we can represent the 
result by 

cfadgbeh 

where each letter represents an octal digit having the same value (0 or 1) as 
the bit originally represented by the same letter. Multiplying this by 
llllllllg generates the following partial products: 

cfadgbeh 
cfadgbeh 
cfadgbeh 
cfadgbeh 
cfadgbeh 
cfadgbeh 
cfadgbeh 
cfadgbeh 

Since any digit is at most 1 , there can be no carry out of any column with 
fewer than eight digits. Hence the octal digit produced by summing the 
center column (the one containing all the bits of the character) is even or 
odd as the sum of the bits is even or odd. Thus its least significant bit (bit 
14 of the low order word in the product) is the parity of the character, if 
even, 1 if odd. 

The above may seem a very complicated procedure to do something 
trivial, but it is effected by this quite simple sequence (with the character 



2.5 FIXED POINT ARITHMETIC 2-31 

right-justified in AC) : 

IMULI AC, 200401 
AND AC.ONES 
IMUL AC, ONES 



ONES: 11111111 

where the parity is indicated by AC bit 14. Of course, following the IMUL 
would be a test instruction to check the value of the bit. 



Arithmetic Shifting 

These two instructions produce an arithmetic shift right or left of the num- 
ber in AC or the double length number in accumulators A and A + 1 . Shifting 
is the movement of the contents of a register bit-to-bit. The operation dis- 
cussed here is similar to logical shifting [see 2.4 and the illustration on 
page 2-24] , but in an arithmetic shift only the magnitude part is shifted - 
the sign is unaffected. In a double length number the 70-bit string made up 
of the magnitude parts of the two words is shifted, but the sign of the low 
order word is made equal to the sign of the high order word. 

Null bits are brought in at the end being vacated: a left shift brings in Os at 
the right, whereas a right shift brings in the equivalent of the sign bit at the 
left. In either case, information shifted out at the other end is lost. A single 
shift left is equivalent to multiplying the number by 2 (provided no bit of 
significance is shifted out); a shift right divides the number by 2. 

The number of places shifted is specified by the result of the effective 
address calculation taken as a signed number (in twos complement notation) 
modulo 2 8 in magnitude. In other words the effective shift E is the number 
composed of bit 18 (which is the sign) and bits 28-35 of the calculation 
result. Hence the programmer may specify the shift directly in the instruc- 
tion (perhaps indexed) or give an indirect address to be used in calculating 
the shift. A positive E produces motion to the left, a negative E to the right; 
E is thus the power of 2 by which the number is multiplied. Maximum 
movement is 255 places. 



ASH Arithmetic Shift Left: 1.62 (1.73) + .\5\E\ MS 

Right: 1.46(1.57) + .\5\E\ns 



240 


A 


1 


X 


Y 



89 121314 1718 35 

Shift AC arithmetically the number of places specified by E. Do not shift 
bit 0. If E is positive, shift left bringing Os into bit 35 ; data shifted out of bit 

1 is lost; set Overflow if any bit of significance is lost (a 1 in a positive num- 
ber, a in a negative one). If E is negative, shift right bringing Os into bit 1 
if AC is positive, Is if negative; data shifted out of bit 35 is lost. 



2-32 



CENTRAL PROCESSOR 



2.6 



ASHC Arithmetic Shift Combined Left: 
Right: 


2.00(2.11) + 
1.84(1.95) + 


.15|ljus 
.15||MS 


244 A i 


' X 


Y 





89 



12 13 14 



17 18 



35 



Concatenate the magnitude portions of accumulators A and A + 1 with A on 
the left, and shift the 70-bit combination in bits 1-35 and 37-71 the num- 
ber of places specified by E. Do not shift AC bit 0, but make bit of AC 
^4 + 1 equal to it if at least one shift occurs (ie if E is nonzero). If E is posi- 
tive, shift left bringing Os into bit 71 (bit 35 of AC ,4 + 1); bit 37 (bit 1 of AC 
A + l) is shifted into bit 35; data shifted out of bit 1 is lost; set Overflow if 
any bit of significance is lost (a 1 in a positive number, a in a negative one). 
If E is negative, shift right bringing Os into bit 1 if AC is positive, 1 s if nega- 
tive; bit 35 is shifted into bit 37; data shifted out of bit 71 is lost. 



V 



A subtraction involving two 
like-signed numbers whose 
exponents are equal and 
whose fractions differ only in 
the LSB gives a result con- 
taining only one bit of signi- 
ficance. 



2.6 FLOATING POINT ARITHMETIC 

For floating point arithmetic the PDF- 10 has instructions for scaling the 
exponent (which is multiplication of the entire number by a power of 2) 
and negating double length numbers as well as for performing addition, sub- 
traction, multiplication and division of numbers in floating point format. 
All instructions treated here interpret all operands as floating point numbers 
in the format given in 1.1, and generate results in that format. The reader 
is strongly advised to reread 1.1 if he does not remember the format in 
detail. 

For the four standard arithmetic operations the program can select wheth- 
er or not the result shall be rounded. Rounding produces the greatest con- 
sistent precision using only single length operands. Instructions without 
rounding have a "long" mode, which supplies a two-word result for greater 
precision; the other modes save time in one-word operations where rounding 
is of no significance. 

Actually the result is formed in a double length register in addition, sub- 
traction and multiplication, wherein any bits of significance in the low order 
part supply information for normalization, and then for rounding if re- 
quested. Consider addition as an example. Before adding, the processor 
right shifts the fractional part of the operand with the smaller exponent until 
its bits correctly match the bits of the other operand in order of magnitude. 
Thus the smaller operand could disappear entirely, having no effect on the 
result ("result" shall always be taken to mean the information (one word or 
two) stored by the instruction, regardless of the number of significant bits it 
contains or even whether it is the correct answer). Long mode is likely to 
retain information that would otherwise be lost, but in any given mode the 
significance of the result depends on the relative values of the operands. 
Even when both operands contain twenty-seven significant bits, a long addi- 
tion may store two words that together contain only one significant bit. In 
division the processor always calculates a one-word quotient that requires no 



2.6 



FLOATING POINT ARITHMETIC 



2-33 



normalization if the original operands are normalized. An extra quotient bit 
is calculated for rounding when requested ; long mode retains the remainder. 

The processor has four flags, Overflow, Floating Overflow, Floating 
Underflow and No Divide, that indicate when the exponent is too large or 
too small to be accommodated or a division cannot be performed because of 
the relative values of dividend and divisor. Any of these circumstances sets 
Overflow and Floating Overflow. If only these two are set, the exponent of 
the answer is too large; if Floating Underflow is also set, the exponent is too 
small. No Divide being set means the processor failed to perform a division, 
an event that can be produced only by a zero divisor if all nonzero operands 
are normalized. These flags can be read and controlled by certain program 
control instructions [2.9] , and Overflow and Floating Overflow are avail- 
able as processor conditions (via in-out instructions [2.14]) that can 
request a priority interrupt if enabled. The conditions detected can only set 
the flags and the hardware does not clear them, so the program must clear 
them before a floating point instruction if they are to give meaningful infor- 
mation about the instruction afterward. However, the program can check 
the flags following a series of instructions to determine whether the entire 
series was free of the types of error detected. 

The floating point hardware functions at its best if given operands that 
are either normalized or zero, and except in special situations the hardware 
normalizes a nonzero result. An operand with a zero fraction and a nonzero 
exponent can give wild answers in additive operations because of extreme 
loss of significance; eg adding & X 2 2 and X 2 69 gives a zero result, as the 
first operand (having a smaller exponent) looks smaller to the processor and 
is shifted to oblivion. A number with a 1 in bit and Os in bits 9-35 is not 
simply an incorrect representation of zero, but rather an unnormalized 
"fraction" with value - 1 . This unnormalized number can produce an incor- 
rect answer in any operation. Use of other unnormalized operands simply 
causes loss of significant bits, except in division where they can prevent its 
execution because they can satisfy a no-divide condition that is impossible 
for normalized numbers. 



The processor normalizes the 
result by shifting the fraction 
and adjusting the exponent to 
compensate for the change in 
value. Each shift and accom- 
panying exponent adjustment 
thus multiply the number 
both by 2 and by l h. simulta- 
neously, leaving its value un- 
changed. 



Scaling 

One floating point instruction is in a category by itself: it changes the 
exponent of a number without changing the significance of the fraction. In 
other words it multiplies the number by a power of 2, and is thus analogous 
to arithmetic shifting of fixed point numbers except that no information is 
lost, although the exponent can overflow or underflow. The amount added 
to the exponent is specified by the result of the effective address calculation 
taken as a signed number (in twos complement notation) modulo 2 8 in mag- 
nitude. In other words the effective scale factor E is the number composed 
of bit 18 (which is the sign) and bits 28-35 of the calculation result. Hence 
the programmer may specify the factor directly in the instruction (perhaps 
indexed) or give an indirect address to be used in calculating it. A positive E 
increases the exponent, a negative E decreases it; E is thus the power of 2 by 
which the number is multiplied. The scale factor lies in the range -256 to 
+255. 



2-34 



CENTRAL PROCESSOR 



2.6 



TV is the number of left shifts 
needed to normalize the 
result. 



This instruction can be used 
to float a fixed number with 
27 or fewer significant bits. 
To float an integer contained 
within AC bits 9-35, 

FSC AC, 233 

inserts the correct exponent 
to move the binary point 
from the right end to the left 
of bit 9 and then normalizes 
(233 8 = 155,o = 128 + 27). 



FSC 



Floating Scale 



2.75(2.86)4- .257V jus 



132 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



If the fractional part of AC is zero, clear AC. Otherwise add the scale factor 
given by E to the exponent part of AC (thus multiplying AC by 2 ), normal- 
ize the resulting word bringing Os into bit positions vacated at the right, and 
place the result back in AC. 

NOTE 

A negative E is represented in standard twos com- 
plement notation, but the hardware compensates 
for this when scaling the exponent. 

If the exponent after normalization is > 127, set Overflow and Floating 
Overflow; the result stored has an exponent 256 less than the correct one. 
If < -128, set Overflow, Floating Overflow and Floating Underflow; the 
result stored has an exponent 256 greater than the correct one. 



In the hardware the rounding 
operation is actually some- 
what more complex than 
stated here. If the result is 
negative, the hardware com- 
bines rounding with placing 
the high order word in twos 
complement form by decreas- 
ing its magnitude if the low 
order part is < HLSB. More- 
over an extra single-step re- 
normalization occurs if the 
rounded word is no longer 
normalized. 

Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /us in memory 
and both modes. 

When E addresses a fast 
memory location, a floating 
point instruction with round- 
ing takes .34 ps less than the 
time listed in basic mode, .80 
(.69) MS less in memory or 
both mode. 



Operations with Rounding 

There are four instructions that use only one-word operands and store a 
single-length rounded result. Rounding is away from zero: if the part of the 
normalized answer being dropped (the low order part of the fraction) is 
greater than or equal in magnitude to one half the LSB of the part being 
retained, the magnitude of the latter part is increased by one LSB. 

The rounding instructions have four modes that determine the source of 
the non-AC operand and the destination of the result. These modes are like 
those of logic and fixed point arithmetic, including an immediate mode that 
allows the instruction to carry an operand with it. 



Mode 

Basic 

Immediate 
Memory 
Both 



Suffix 

I 

M 

B 



Source ofnon- 
A C operand 



The word.E,0 
E 
E 



Destination 
of result 

AC 

AC 

E 

AC and E 



Note however that floating point immediate uses E,0 as an operand, not 
0, E. In other words the half word E is interpreted as a sign, an 8-bit expo- 
nent, and a 9-bit fraction. 

The time required is a function of the number N of left shifts needed for 
normalization. Brackets enclose the additional time required when rounding 
actually changes the high order word. 

In each of these instructions, the exponent that results from normaliza- 



MAY 1968 



2.6 



FLOATING POINT ARITHMETIC 



2-35 



tion and rounding is tested for overflow or underflow. If the exponent is 
> 127, set Overflow and Floating Overflow; the result stored has an expo- 
nent 256 less than the correct one. If <-128, set Overflow, Floating Over- 
flow and Floating Underflow; the result stored has an exponent 256 greater 
than the correct one. 



FADR 



Floating Add and Round 



144 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



1718 



35 



Floating add the operand specified by M to AC. If the double length fraction 
in the sum is zero, clear the specified destination. Otherwise normalize the 
double length sum bringing Os into bit positions vacated at the right, round 
the high order part, test for exponent overflow or underflow as described 
above, and place the result in the specified destination. 

FADR Floating Add and Round 144 

4.46 (4.68) + .\5D + .25N [+.96] jus 
FADR I Floating Add and Round Immediate 145 

3.70 (3.81) + .15D + . 257V [+.96] /us 
FADRM Floating Add and Round to Memory 146 

5.43 (5.65) + A5D + .257V [+.96] jus 
FADRB Floating Add and Round to Both 147 

5.43 (5.65) + .15D + .257V [+.96] /us 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise D = 0. 



FSBR 



Floating Subtract and Round 



154 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating subtract the operand specified by M from AC. If the double length 
fraction in the difference is zero, clear the specified destination. Otherwise 
normalize the double length difference bringing Os into bit positions vacated 
at the right, round the high order part, test for exponent overflow or under- 
flow as described above, and place the result in the specified destination. 



FSBR Floating Subtract and Round 

4.64 (4.86) + A5D + 
FSBR I Floating Subtract and Round Immediate 

3.88(3.99) + A5D + 
FSBRM Floating Subtract and Round to Memory 

5.61 (5.83) + .15Z) + 
FSBRB Floating Subtract and Round to Both 

5.61 (5.83) + 



154 
157V [+.96] /us 

155 
15/V[+.96] jus 

156 
15/V[+.96] /us 

157 
157V [+.96] /us 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise D = 0. 



2-36 



Use of normalized operands 
requires at most one normali- 
zation step, for the result. If 
unnormalized operands are 
used, all times must be in- 
creased by .25./V. 



FMPR 



CENTRAL PROCESSOR 

Floating Multiply and Round 



2.6 



1 64 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating Multiply AC by the operand specified by M. If the double length 
fraction in the product is zero, clear the specified destination. Otherwise 
normalize the double length product bringing Os into bit positions vacated at 
the right, round the high order part, test for exponent overflow or underflow 
as described above, and place the result in the specified destination. 



FMPR Floating Multiply and Round 

10.29(10.51) 
FMPRI Floating Multiply and Round Immediate 

8.36(8.47) 
FMPRM Floating Multiply and Round to Memory 

11.26(11.48) 
FMPRB Floating Multiply and Round to Both 

\ 11.26(11.48) 

Timing. The times given above are average for normalized 
Refer to the description of MUL [ 2.5] for the timing effects of 
plication algorithm. Minimum times with a zero multiplier are 



164 
[+.96] jus 

165 
[+.96] MS 

166 
[+.96] MS 

167 
[+.96] MS 

operands, 
the multi- 



FMPR 
FMPRI 
FMPRM 
FMPRB 



8.47(8.69) [+.96] MS 
7.71 (7.82) [+.96] MS 
9.44(9.66) [+.96] MS 
9.44(9.66) [+.96] MS 



These must be increased by .13 MS for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



Division fails if the divisor is 
zero, but the no-divide condi- 
tion can otherwise be satisfied 
only if at least one operand is 
unnormalized. 



FDVR 



Floating Divide and Round 



174 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



If the magnitude of the fraction in AC is greater than or equal to twice that 
of the fraction in the operand specified by M, set Overflow, Floating Over- 
flow and No Divide, and go immediately to the next instruction without 
affecting the original AC or memory operand in any way.' 

If the division can be performed, floating divide AC by the operand spec- 
ified by M, calculating a quotient fraction of 28 bits (this includes an extra 
bit for rounding). If the fraction is zero, clear the specified destination. 
Otherwise the single-length quotient will already be normalized if the orig- 
inal operands were normalized; in this case, round it using the extra bit cal- 
culated. If the quotient is not normalized, do so bringing first the extra 
calculated bit and then Os into bit positions vacated at the right. Test for 



2.6 



FLOATING POINT ARITHMETIC 



2-37 



exponent overflow or underflow as described above, and place the result in 
the specified destination. 



FDVR Floating Divide and Round 

FDVRI Floating Divide and Round Immediate 

FDVRM Floating Divide and Round to Memory 

FDVRB Floating Divide and Round to Both 



174 
14.1 (14.3) jus 

175 
13.3 (13.4) jus 

176 
15.1 (15.3) MS 

177 
15.1 (15.3) MS 



If unnormalized operands are 
used, all times must be in- 
creased by .257V. If the divi- 
sion is not performed, only 
3.5-4 /us are required. 



Operations without Rounding 

Instructions that do not round are faster for processing floating point num- 
bers with fractions containing fewer than 27 significant bits. On the other 
hand the long mode provides double precision or allows the programmer to 
use his own method of rounding. Besides the four usual arithmetic opera- 
tions with normalization, there are two nonnormalizing instructions that 
facilitate double precision arithmetic [2.1 1 gives examples of double preci- 
sion floating point routines] . These two instructions have no modes. 



DFN 



Double Floating Negate 



3.43 (3.54) MS 



131 | A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Negate the double length floating point number composed of the contents of 
AC and location E with AC on the left. Do this by taking the twos comple- 
ment of the number whose sign is AC bit 0, whose exponent is in AC bits 
1-8, and whose fraction is the 54-bit string in bits 9-35 of AC and location 
E. Place the high order word of the result in AC; place the low order part of 
the fraction in bits 9-35 of location E without altering the original contents 
of bits 0-8 of that location. 



Usually the double length 
number is in two adjacent 
accumulators, and E equals 
A+l. In this case DFN takes 
only 2. 89 (3.11) MS. 



UFA 



Unnormalized Floating Add 



130 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



Floating add the contents of location E to AC. If the double length fraction 
in the sum is zero, clear accumulator A + l. Otherwise normalize the sum 
only if the magnitude of its fractional part is > 1 , and place the high order 
part of the result in AC A + l. The original contents of AC ana are 
unaffected. 



4.62(4.84) + A5D fis D is the difference between 

the operand exponents pro- 
vided that difference is < 63. 
Otherwise D = 0. 

When E addresses a fast 
memory location, UFA takes 
.34 M S l ess than the time 
given. 



35 



f\C 



E 







MAY 1968 






2-38 

The exponent of the sum is 
equal to that of the larger 
summand unless addition of 
the fractions overflows, in 
which case it is greater by 1. 
Exponent overflow can occur 
only in the latter case. 



CENTRAL PROCESSOR 



2.6 



NOTE 

The result is placed in accumulator A+l . This is 
the only arithmetic instruction that stores the 
result in a second accumulator, leaving the original 
operands intact. 

If the exponent of the sum following the one-step normalization is > 127, 
set Overflow and Floating Overflow; the result stored has an exponent 256 
less than the correct one. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /us in memory 
and both modes. 

When E addresses a fast 
memory location, a floating 
point instruction without 
rounding takes .34 MS less 
than the time listed in basic 
or long mode, .80 (.69) /us 
less in memory or both mode. 



The remaining floating point instructions perform the four standard arith- 
metic operations with normalization but without rounding. All use AC and 
the contents of location E as operands and have four modes. 



Mode 

Basic 
Long 



Suffix 
L 



Effect 

High order word of result stored in AC. 

In addition, subtraction and multiplica- 
tion, the two-word result (in th^d^ouble 
length format described inB I is 
stored in accumulators A ancft^^^n 
division the dividend is the double leneth 



Memory M High order word of result store/d in E. 

Both B 'High order word of result stored in AC 

and E. ^ifc 

l tw^cT v s*< a. . 

-^UMbw 'rewas&fa v 

In each of these instructions, the exponent that results, from normaliza- 
tion is tested for overflow or underflow. If the exponent is\Z> 127, set Over- 
flow and Floating Overflow; the result stored has an exponent 256 less than 
the correct one. If < -128, set Overflow, Floating Overflow and Floating 
Underflow; the result stored has an exponent 256 greater than the correct 
one. 

The time required is a function of the number N of left shifts needed for 
normalization. 



FAD 



Floating Add 



140 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



1718 



35 



Floating add the contents of location E to AC. If the double length fraction 
in the sum is zero, clear the destination specified by M, clearing both accu- 



2.6 



FLOATING POINT ARITHMETIC 



2-39 



mulators in long mode. Otherwise normalize the double length sum bringing 
Os into bit positions vacated at the right, test for exponent overflow or 
underflow as described above, and place the high order word of the result in 
the specified destination. 

In long mode if the exponent of the sum is > 1 54 ( 1 27 + 27) or < - 1 1 
(-128 + 27) or the low order half of the fraction is zero, clear AC A + \. 
Otherwise place a low order word for a double length result in A + l by 
putting a in bit 0, an exponent in positive form 27 less than the exponent 
of the sum in bits 1 -8, and the low order part of the fraction in bits 9-35. 



FAD Floating Add 

F A D L Floating Add Long 

FADM Floating Add to Memory 

FADB Floating Add to Both 



140 
4.46 (4.68) + .15D + .257V jus 

141 
5.3 1 (5.53) + .15D + . 257V /us 

142 
5.43 (5.65) + .15D + .25N (is 

143 
5.43(5.65) + .15> + .25N us 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise D = 0. 



FSB 



Floating Subtract 



150 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating subtract the contents of location E from AC. If the double length 
fraction in the difference is zero, clear the destination specified by M, clear- 
ing both accumulators in long mode. Otherwise normalize the double length 
difference bringing Os into bit positions vacated at the right, test for expo- 
nent overflow or underflow as described above, and place the high order 
word of the result in the specified destination. 

In long mode if the exponent of the difference is > 154 (127 + 27) or 
< -101 (-128 + 27) or the low order half of the fraction is zero, clear AC 
A + 1 . Otherwise place a low order word for a double length result in A + 1 by 
putting a in bit 0, an exponent in positive form 27 less than the exponent 
of the difference in bits 1 -8, and the low order part of the fraction in bits 
9-35. 



FSB Floating Subtract 

FSBL Floating Subtract Long 

FSBM Floating Subtract to Memory 

FSBB Floating Subtract to Both 



150 
4.64 (4.86) + A5D + .25N jus 

151 
5.49(5.71) + A5D + .25N us 

152 
5.61 ( 



153 



5.61 (5.83) + A5D + .25N 



D is the difference between 
the operand exponents pro- 
vided that difference is <63. 
Otherwise D = 0. 



2-40 



CENTRAL PROCESSOR 



2.6 



FMP 



Use of normalized operands 
requires at most one normali- 
zation step for the result. If 
unnormalized operands are 
used, all times must be in- 
creased by .25N. 



Floating Multiply 



1 60 


M 


A 


1 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating multiply AC by the contents of location E. If the double length 
fraction in the product is zero, clear the destination specified by M, clearing 
both accumulators in long mode. Otherwise normalize the double length 
product bringing Os into bit positions vacated at the right, test for exponent 
overflow or underflow as described above, and place the high order word of 
the result in the specified destination. 

In long mode if the exponent of the product is > 154 (127 + 27) or 
< -101 (-128 + 27) or the low order half of the fraction is zero, clear AC 
A + l. Otherwise place a low order word for a double length result in ^4 + 1 
by putting a in bit 0, an exponent in positive form 27 less than the 
exponent of the product in bits 1-8, and the low order part of the fraction 
in bits 9-35. 



FMP Floating Multiply 

FMPL Floating Multiply Long 

FMPM Floating Multiply to Memory 

FMPB Floating Multiply to Both 



160 10.29 (10.51) MS 

161 11. 14(1 1.36) /us 

162 11. 26 (11. 48) MS 

163 11. 26 (11.48) MS 



Timing. The times given above are average for normalized operands. 
Refer to the description of MUL [ 2.5] for the timing effects of the multi- 
plication algorithm. Minimum times with a zero multiplier are 



FMP 
FMPL 
FMPM 
FMPB 



8.47 (8.69) MS 
9.32 (9.54) MS 
9.44 (9.66) MS 
9.44 (9.66) MS 



These must be increased by .13 MS for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



Division fails if the divisor is 
zero, but the no-divide condi- 
tion can otherwise be satisfied 
only if at least one operand is 
unnormalized. 



FDV 



Floating Divide 



1 70 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



If the magnitude of the fraction in AC is greater than or equal to twice that 
of the fraction in location E, set Overflow, Floating Overflow and No Divide, 
and go immediately to the next instruction without affecting the original AC 
or memory operand in any way. 

If division can be performed, floating divide the AC operand by the 
contents of location E. In long mode the AC operand (the dividend) is the 
double length number in accumulators A and A + \ ; in other modes it is the 
single word in AC. Calculate a quotient fraction of 27 bits. If the fraction 



2.7 



ARITHMETIC TESTING 



2-41 



is zero, clear the destination specified by M, clearing both accumulators in 
long mode if the double length dividend was zero. A quotient with a non- 
zero fraction will already be normalized if the original operands were nor- 
malized; if it is not, normalize it bringing Os into bit positions vacated at the 
right. Test for exponent overflow or underflow as described above, and 
place the single length quotient part of the result in the specified destination. 
In long mode calculate the exponent for the fractional remainder from the 
division according to the relative magnitudes of the fractions in dividend and 
divisor: if the dividend was greater than or equal to the divisor, the exponent 
of the remainder is 26 less than that of the dividend, otherwise it is 27 less. 
If the remainder exponent is > 1 27 or < - 1 28 or the fraction is zero, clear 
AC A + 1 . Otherwise place the floating point remainder (exponent and frac- 
tion) with the sign of the dividend in AC A + 1 . 



FDV Floating Divide 

FDVL Floating Divide Long 

FDVM Floating Divide to Memory 

FDVB Floating Divide to Both 



170 
171 

172 
173 



14.1 (14.3) MS 
15.6 (15.8) MS 
15.1 (15.3) MS 
15.1 (15.3) MS 



In long mode a nonzero un- 
normalized dividend whose 
entire high order fraction is 
zero produces a zero quo- 
tient. In this case the second 
AC receives rubbish. 



If unnormalized operands are 
used, all times must be in- 
creased by .25N. If the divi- 
sion is not performed, only 
4-4.5 /is are required. 



2.7 ARITHMETIC TESTING 

These instructions may jump or skip depending on the result of an arithmetic 
test and may first perform an arithmetic operation on the test word. Two of 
the instructions have no modes. 



AOBJP Add One to Both Halves of AC and Jump if Positive 1.68 (1.79) MS 



252 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC and place the result back in AC. If the result is greater 
than or equal to zero (ie if bit is 0, and hence a negative count in the left 
half has reached zero or a positive count has not yet reached 2 17 ), take the 
next instruction from location E and continue sequential operation from 
there. 



AOBJN 



Add One to Both Halves of AC and Jump if Negative 1.68 (1.79) MS 



253 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC and place the result back in AC. If the result is less 
than zero (ie if bit is 1 , and hence a negative count in the left half has not 
yet reached zero or a positive count has reached 2 17 ), take the next instruc- 
tion from location E and continue sequential operation from there. 



2-42 CENTRAL PROCESSOR 2.7 

The incrementing of both halves of AC simultaneously is effected by adding 
1 000001 8 . A count of -2 in AC left is therefore increased to zero if 2 18 - 1 
is incremented in AC right. 

These two instructions allow the program to keep a control count in the 
left half of an index register and require only one data transfer to initialize. 
Problem: Add 3 to each location in a table of TV entries starting at TAB. 
Only four instructions are required. 

MOVSI XR -N ;Put -TV in XR left (clear XR right) 

MOVEI AC, 3 ;Put3inAC 

ADDM AC,TAB(XR) ;Add 3 to entry 

AOBJN XR,.-1 ;Update XR and go back unless all 

;entries accounted for 



The eight remaining instructions jump or skip if the operand or operands 
satisfy a test condition specified by the mode. 

Mode Suffix 

Never 

Less L 

Equal E 

Less or Equal LE 

Always A 

Greater or Equal GE 

Not Equal N 

Greater G 

Instructions with one operand compare AC or the contents of location E 
with zero, those with two compare AC with E or the contents of location E. 
The processor always makes the comparison even though the result is used in 
only six of the modes. If the mnemonic has no suffix there is never any 
program control function, and the instruction may be a no-op; an A suffix 
produces an unconditional jump or skip the action is always taken regard- 
less of how the two quantities compare. 



CAI Compare AC Immediate and Skip if Condition 1 .68 ( 1 .79) /us 

Satisfied 



30 


M 


A 


I 


X 


Y 



56 89 121314 1718 35 

Compare AC with E (ie with the word 0, E) and skip the next instruction in 
sequence if the condition specified by M is satisfied. 



2.7 



ARITHMETIC TESTING 



2-43 



CAI 


Compare AC Immediate but Do Not Skip 300 


CAIL 


Compare AC Immediate and Skip if AC Less than E 301 


CAIE 


Compare AC Immediate and Skip if Equal 302 


CAILE 


Compare AC Immediate and Skip if AC Less than 303 
or Equal to E 


CAIA 


Compare AC Immediate but Always Skip 304 


CAIGE 


Compare AC Immediate and Skip if AC Greater than 305 
or Equal to E 


CAIN 


Compare AC Immediate and Skip if Not Equal 306 


CAIG 


Compare AC Immediate and Skip if AC Greater than E 307 


CAM 


Compare AC with Memory and Skip if Condition 2.53 (2.75) /us 
Satisfied 


31 


MAI 


X Y 


56 89 121314 1718 35 

Compare AC with the contents of location E and skip the next instruction in 
sequence if the condition specified by M is satisfied. The pair of numbers 
compared may be either both fixed or both normalized floating point. 


CAM 


Compare AC with Memory but Do Not Skip 310 


CAML 


Compare AC with Memory and Skip if AC Less 3 1 1 


CAME 


Compare AC with Memory and Skip if Equal 312 


CAMLE 


Compare AC with Memory and Skip if AC Less . 313 
or Equal 


CAMA 


Compare AC with Memory but Always Skip 314 


CAMGE 


Compare AC with Memory and Skip if AC Greater 315 
or Equal 


CAMN 


Compare AC with Memory and Skip if Not Equal 3 1 6 


CAMG 


Compare AC with Memory and Skip if AC Greater 3 1 7 


JUMP 


Jump if AC Condition Satisfied 1 .68 ( 1 .79) //s 


32 


M A I 


X Y 


56 89 1213 


14 1718 35 



CAI is a no-op. 



Compare AC (fixed or floating) with zero, and if the condition specified by 
M is satisfied, take the next instruction from location E and continue 
sequential operation from there. 



JUMP Do Not Jump 

JUMPL Jump if AC Less than Zero 

JUMPE Jump if AC Equal to Zero 



320 
321 

322 



When E addresses a fast mem- 
ory location, this instruction 
takes .34 jus less than the time 
given. 



CAM is a no-op that refer- 
ences memory. 



JUMP is a no-op (instruction 
code 320 has this mnemonic 
for symmetry). 



2-44 



CENTRAL PROCESSOR 



2.7 



JUMPLE Jump if AC Less than or Equal to Zero 

JUMPA Jump Always 

JUMPGE Jump if AC Greater than or Equal to Zero 

JUMPN Jump if AC Not Equal to Zero 

JUMPG Jump if AC Greater than Zero 



323 
324 

325 
326 
327 



When E addresses a fast mem- 
ory location, this instruction 
takes .34 /us less than the time 
given. 

If A is zero, SKIP is a no-op; 
otherwise it is equivalent to 
MOVE. (Instruction code 330 
has mnemonic SKIP for sym- 
metry.) 



SKIPA is a convenient way to 
load an accumulator and skip 
over an instruction upon en- 
tering a loop. 



SKIP 



Skip if Memory Condition Satisfied 



2.39 (2.61) 



33 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Compare the contents (fixed or floating) of location E with zero, and skip 
the next instruction in sequence if the condition specified by M is satisfied. 
If A is nonzero also place the contents of location E in AC. 



SKIP Do Not Skip 

SKIPL Skip if Memory Less than Zero 

SKIPE Skip if Memory Equal to Zero 

SKIPLE Skip if Memory Less than or Equal to Zero 

SKIPA Skip Always 

SKIPGE Skip if Memory Greater than or Equal to Zero 

SKIPN Skip if Memory Not Equal to Zero 

SKIPG Skip if Memory Greater than Zero 



330 
331 

332 
333 
334 
335 
336 
337 



AOJ 



Add One to AC and Jump if Condition Satisfied 



56 



89 



12 13 14 



J7 18 



1.68 (1.79) /US 



34 


M 


A 


I 


X 


Y 



35 



Increment AC by one and place the result back in AC. Compare the result 
with zero, and if the condition specified by M is satisfied, take the next in- 
struction from location E and continue sequential operation from there. If 
AC originally contained 2 35 1, set the Overflow and Carry 1 flags; if 1, 
set Carry and Carry 1 . 

AOJ Add One to AC but Do Not Jump 340 

AOJL Add One to AC and Jump if Less than Zero 341 

AOJE Add One to AC and Jump if Equal to Zero 342 

AOJLE Add One to AC and Jump if Less than or Equal to Zero 343 

AOJA Add One to AC and Jump Always 344 

AOJGE Add One to AC and Jump if Greater than or Equal 345 

to Zero 

AOJN Add One to AC and Jump if Not Equal to Zero 346 

AOJG Add One to AC and Jump if Greater than Zero 347 



2.7 



ARITHMETIC TESTING 



2-45 



AOS 



Add One to Memory and Skip if Condition Satisfied 2.94 (3.05) jus 



35 


M 


A 


/ 


X 


Y 



56 



89 



12 13 14 



1718 



35 



Increment the contents of location E by one and place the result back in E. 
Compare the result with zero, and skip the next instruction in sequence if 
the condition specified by M is satisfied. If location E originally contained 
2 35 - 1, set the Overflow and Carry 1 flags; if -1, set Carry and Carry 1. 
If A is nonzero also place the result in AC. 

AOS Add One to Memory but Do Not Skip 350 

AOSL Add One to Memory and Skip if Less than Zero 35 1 

AOSE Add One to Memory and Skip if Equal to Zero 352 

AOSLE Add One to Memory and Skip if Less than or Equal 353 

to Zero 

AOSA Add One to Memory and Skip Always 354 

AOSGE Add One to Memory and Skip if Greater than or 355 

Equal to Zero 

AOSIM Add One to Memory and Skip if Not Equal to Zero 356 

AOSG Add One to Memory and Skip if Greater than Zero 357 



Keeping the count in fast 
memory saves .54 (.43) /as; 
keeping it in a different mem- 
ory from the instruction saves 
.20 (.09) jus. 



SOJ Subtract One from AC and Jump if Condition 

Satisfied 



1.68 (1.79) jus 



36 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



1718 



35 



Decrement AC by one and place the result back in AC. Compare the result 
with zero, and if the condition specified by M is satisfied, take the next in- 
struction from location E and continue sequential operation from there. If 
AC originally contained -2 35 , set the Overflow and Carry flags; if any other 
nonzero number, set Carry and Carry 1 . 

SOJ Subtract One from AC but Do Not Jump 360 

SOJL Subtract One from AC and Jump if Less than Zero 361 

SOJE Subtract One from AC and Jump if Equal to Zero 362 

SOJLE Subtract One from AC and Jump if Less than or 363 

Equal to Zero 

SOJA Subtract One from AC and Jump Always 364 

SOJGE Subtract One from AC and Jump if Greater than or 365 

Equal to Zero 

SOJN Subtract One from AC and Jump if Not Equal to Zero 366 

SOJG Subtract One from AC and Jump if Greater than Zero 367 



2-46 

Keeping the count in fast 
memory saves .54 (.43) us; 
keeping it in a different mem- 
ory from the instruction saves 
.20 (.09) MS. 



CENTRAL PROCESSOR 



SOS 



Subtract One from Memory and Skip if Condition 
Satisfied 



2.7 
2.94 (3.05) MS 



37 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Decrement the contents of location E by one and place the result back in E. 
Compare the result with zero, and skip the next instruction in sequence if 
the condition specified by M is satisfied. If location E originally contained 
-2 35 , set the Overflow and Carry flags; if any other nonzero number, set 
Carry and Carry 1 . If A is nonzero also place the result in AC. 

SOS Subtract One from Memory but Do Not Skip 370 

SOSL Subtract One from Memory and Skip if Less than Zero 371 

SOSE Subtract One from Memory and Skip if Equal to Zero 372 

SOSLE Subtract One from Memory and Skip if Less than or 373 

Equal to Zero 

SOSA Subtract One from Memory and Skip Always 374 

SOSGE Subtract One from Memory and Skip if Greater 375 

than or Equal to Zero 

SOSN Subtract One from Memory and Skip if Not Equal 376 

to Zero 

SOSG Subtract One from Memory and Skip if Greater 377 

than Zero 



This procedure is invalid if 
the programmer is making use 
of the drum split feature 
(which is not used by any 
DEC equipment). 



Some of these instructions are useful for determining the relative values of 
fixed and floating point numbers; others are convenient for controlling 
iterative processes by counting. AOSE is especially useful in an interlock 
procedure in a multiprocessor system. Suppose memory contains a routine 
that must be available to two processors but cannot be used by both at once. 
When one processor finishes the routine it sets location LOCK to - 1 . Either 
processor can then test the interlock and make it busy with no possibility of 
letting the other one in, as AOSE cannot be interrupted once it starts to 
modify the addressed location. 



AOSE LOCK 
JRST .-1 



SETOM LOCK 



;Skip to interlocked code only if 
;LOCK is zero after addition 
; Interlocked code starts here 

;Unlock 



Since it takes several days to count to 2 36 , it is alright to keep testing the 
lock. 



2.8 LOGICAL TESTING AND MODIFICATION 

2.8 LOGICAL TESTING AND MODIFICATION 



2-47 



These eight instructions use a mask to modify and/or test selected bits in 
AC. The bits are those that correspond to Is in the mask and they are 
referred to as the "masked bits". The programmer chooses the mask, the 
way in which the masked bits are to be modified, and the condition the 
masked bits must satisfy to produce a skip. 

The basic mnemonics are three letters beginning with T. The second letter 
selects the mask and the manner in which it is used. 



Mask 
Right 

Left 

Direct 

Swapped 



Letter 
R 

L 
D 

S 



Effect 

AC right is masked by E (AC is masked 
by the word 0,E) 

AC left is masked by E (AC is masked by 
the word ,0) 

AC is masked by the contents of loca- 
tion E 

AC is masked by the contents of loca- 
tion E with left and right halves inter- 
changed 



The third letter determines the way in which those bits selected by the mask 
are modified. 



Modification 

No 
Zeros 

Complement 
Ones 



Letter 

N 
Z 
C 

o 



Effect on AC 

None 

Places Os in all masked bit positions 
Complements all masked bits 
Places Is in all masked bit positions 



An additional letter may be appended to indicate the mode, which spec- 
ifies the condition the masked bits must satisfy to produce a skip. 



Mode 

Never 
Equal 
Always 
Not Equal 



Suffix 

E 
A 

N 



Effect 

Never skip 

Skip if all masked bits equal 

Always skip 

Skip if not all masked bits equal 
(at least one bit is 1) 



If the mnemonic has no suffix there is never any skip, and the instruction is 
a no-op if there is also no modification; an A suffix produces an uncondi- 
tional skip the skip always occurs regardless of the state of the masked 
bits. Note that the skip condition must be satisfied by the state of the 
masked bits prior to any modification called for by the instruction. 



If a direct or swapped mask is 
taken from a fast memory 
location, a test instruction 
takes .34 ;us less than the 
time listed. 



These mode names are con- 
sistent with those for arith- 
metic testing and derive from 
the test method, which ands 
AC with the mask and tests 
whether the result is equal to 
zero or is not equal to zero. 
The programmer may find it 
convenient to think of the 
modes as Every and Not 
Every: every masked bit is 
or not every masked bit is 0. 



2-48 



TRN is a no-op. 



CENTRAL PROCESSOR 



TRN Test Right, No Modification, and Skip if Condition 

Satisfied 



2.8 
1.85 (1.96) jus 



60 


M 





A 


1 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC right corresponding to Is in E satisfy the condition specified 
by M , skip the next instruction in sequence. AC is unaffected. 



TRN Test Right, No Modification, but Do Not Skip 

TRIME Test Right, No Modification, and Skip if All 

Masked Bits Equal 

TRIM A Test Right, No Modification, but Always Skip 

TRNN Test Right, No Modification, and Skip if Not 

All Masked Bits Equal 



600 
602 

604 
606 



TRZ 



Test Right, Zeros, and Skip if Condition Satisfied 



56 789 



12 13 14 



17 18 



1.85 (1.96) 



62 


M 





A 


I 


X 


Y 



35 



If the bits in AC right corresponding to 1 s in E satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Os; the rest of AC is unaffected. 



TRZ Test Right, Zeros, but Do Not Skip 

TRZE Test Right, Zeros, and Skip if All Masked Bits 

Equaled 

TRZA Test Right, Zeros, but Always Skip 

TRZN Test Right, Zeros, and Skip if Not All Masked 

Bits Equaled 



620 
622 

624 
626 



TRC Test Right, Complement, and Skip if Condition 

Satisfied 



56 789 



12 13 14 



17 18 



1.85 (1.96) MS 



64 


M 





A 


I 


X 


Y 



35 



If the bits in AC right corresponding to Is in E satisfy the condition specified 
by M, skip the next instruction in sequence. Complement the masked AC 
bits; the rest of AC is unaffected. 



TRC Test Right, Complement, but Do Not Skip 

TRCE Test Right, Complement, and Skip if All Masked 

Bits Equaled 

TRCA Test Right, Complement, but Always Skip 

TRCN Test Right, Complement, and Skip if Not All 

Masked Bits Equaled 



640 
642 

644 
646 



2.8 



LOGICAL TESTING AND MODIFICATION 



2-49 



TRO 



Test Right, Ones, and Skip if Condition Satisfied 



1.85 (1.96) jus 



66 


M 





A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC right corresponding to 1 s in E satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Is; the rest of AC is unaffected. 



TRO Test Right, Ones, but Do Not Skip 

TROE Test Right, Ones, and Skip if All Masked Bits 

Equaled 

TRO A Test Right, Ones, but Always Skip 

TRON Test Right, Ones, and Skip if Not All Masked 

Bits Equaled 



660 
662 

664 
666 



TLN Test Left, No Modification, and Skip if Condition 1 .85 ( 1 .96) 

Satisfied 



60 


M 


1 


A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC left corresponding to 1 s in E satisfy the condition specified 
by M, skip the next instruction in sequence. AC is unaffected. 



TLN Test Left, No Modification, but Do Not Skip 

TLN E Test Left, No Modification, and Skip if All 

Masked Bits Equal 

TLNA Test Left, No Modification, but Always Skip 

TLNN Test Left, No Modification, and Skip if Not 

All Masked Bits Equal 



601 
603 

605 

607 



TLN is a no-op. 



TLZ 



Test Left, Zeros, and Skip if Condition Satisfied 



56 789 



12 13 14 



17 18 



1.85 (1.96) MS 



62 


M 


1 


A 


I 


X 


Y 



35 



If the bits in AC left corresponding to 1 s in satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Os; the rest of AC is unaffected. 



TLZ Test Left, Zeros, but Do Not Skip 

TLZE Test Left, Zeros, and Skip if All Masked Bits 

Equaled 

TLZA Test Left, Zeros, but Always Skip 

TLZN Test Left, Zeros, and Skip if Not All Masked 

Bits Equaled 



621 
623 

625 

627 



2-50 



CENTRAL PROCESSOR 



2 
, - 



TLC Test Left, Complement, and Skip if Condition 

Satisfied 



1.85 (1.96) jus 



64 


M 


1 


A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC left corresponding to 1 s in E satisfy the condition specified 
by M, skip the next instruction in sequence. Complement the masked AC 
bits; the rest of AC is unaffected. 



TLC Test Left, Complement, but Do Not Skip 

TLCE Test Left, Complement, and Skip if All Masked 

Bits Equaled 

TLCA Test Left, Complement, but Always Skip 

TLCN Test Left, Complement, and Skip if Not All 

Masked Bits Equaled 



641 
643 

645 
647 



TLO 



Test Left, Ones, and Skip if Condition Satisfied 



56 789 



12 13 14 



17 18 



1.85 (1.96) 



66 


M 


\\ A 


I 


X 


Y 



35 



If the bits in AC left corresponding to Is in satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Is; the rest of AC is unaffected. 



TLO Test Left, Ones, but Do Not Skip 

TLOE Test Left, Ones, and Skip if All Masked Bits 

Equaled 

TLOA Test Left, Ones, but Always Skip 

TLON Test Left, Ones, and Skip if Not All Masked 

Bits Equaled 



661 
663 

665 

667 



TDN is a no-op that refer- 
ences memory. 



TDN Test Direct, No Modification, and Skip if Condition 

Satisfied 



56 789 



12 13 14 



17 18 



2.70 (2.92) MS 



6 1 


M 





A 


I 


X 


Y 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by M, skip the next instruction in sequence. AC is un- 
affected. 



TDN Test Direct, No Modification, but Do Not Skip 

TONE Test Direct, No Modification, and Skip if All 

Masked Bits Equal 
TDNA Test Direct, No Modification, but Always Skip 

TDNN Test Direct, No Modification, and Skip if Not 

All Masked Bits Equal 



610 
612 

614 
616 



2.8 



LOGICAL TESTING AND MODIFICATION 



2-51 



TDZ 



Test Direct, Zeros, and Skip if Condition Satisfied 



2.70 (2.92) MS 



63 


M 





A \I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by M, skip the next instruction in sequence. Change the 
masked AC bits to Os; the rest of AC is unaffected. 



TDZ Test Direct, Zeros, but Do Not Skip 

TDZE Test Direct, Zeros, and Skip if All Masked Bits 

Equaled 

TDZA Test Direct, Zeros, but Always Skip 

TDZIM Test Direct, Zeros, and Skip if Not All Masked 

Bits Equaled 



630 
632 

634 
636 



TDC Test Direct, Complement, and Skip if Condition 2.70(2.92) 

Satisfied 



65 


M 





A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to 1 s in the contents of location E satisfy the 
condition specified by M , skip the next instruction in sequence. Complement 
the masked AC bits; the rest of AC is unaffected. 



TDC Test Direct, Complement, but Do Not Skip 

TDCE Test Direct, Complement, and Skip if All Masked 

Bits Equaled 

TDCA Test Direct, Complement, but Always Skip 

TDCN Test Direct, Complement, and Skip if Not All 

Masked Bits Equaled 



650 
652 

654 
656 



TOO 



Test Direct, Ones, and Skip if Condition Satisfied 



56 789 



12 13 14 



17 18 



2.70 (2.92) MS 



67 


M 





A 


I 


X 


Y 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by M, skip the next instruction in sequence. Change the 
masked AC bits to Is; the rest of AC is unaffected. 



TOO Test Direct, Ones, but Do Not Skip 

TDOE Test Direct, Ones, and Skip if All Masked Bits 

Equaled 

TOO A Test Direct, Ones, but Always Skip 

TD N Test Direct, Ones, and Skip if Not All Masked 

Bits Equaled 



670 
672 

674 
676 



2-52 



TSN is a no-op that refer- 
ences memory. 



CENTRAL PROCESSOR 



TSN Test Swapped, No Modification, and Skip if 

Condition Satisfied 



2.8 
2.70 (2.92) MS 



61 


M 


\ 


A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to 1 s in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. AC is unaffected. 



TSN Test Swapped, No Modification, but Do Not Skip 

TSNE Test Swapped, No Modification, and Skip if All 

Masked Bits Equal 

TSNA Test Swapped, No Modification, but Always Skip 

TSNN Test Swapped, No Modification, and Skip if Not 

All Masked Bits Equal 



611 

613 

615 
617 



TSZ 



Test Swapped, Zeros, and Skip if Condition Satisfied 2.70 (2.92) 



63 | M 


1 


A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to 1 s in the contents of location E with its 
left and right halves swapped satisfy the condition specified by Af, skip the 
next instruction in sequence. Change the masked AC bits to Os; the rest of 
AC is unaffected. 



TSZ Test Swapped, Zeros, but Do Not Skip 

TSZE Test Swapped, Zeros, and Skip if All Masked Bits 

Equaled 

TSZA Test Swapped, Zeros, but Always Skip 

TSZN Test Swapped, Zeros, and Skip if Not All Masked 

Bits Equaled 



631 
633 

635 

637 



TSC 



Test Swapped, Complement, and Skip if Condition 2.70 (2.92) 

Satisfied 



65 


M 


\ 


A 


1 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to 1 s in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. Complement the masked AC bits; the rest of 
AC is unaffected. 



TSC Test Swapped, Complement, but Do Not Skip 

TSCE Test Swapped, Complement, and Skip if All 

Masked Bits Equaled 



651 
653 



2.8 



LOGICAL TESTING AND MODIFICATION 



2-53 



TSCA Test Swapped, Complement, but Always Skip 

TSCN Test Swapped, Complement, and Skip if Not 

All Masked Bits Equaled 



655 
657 



ISO 



Test Swapped, Ones, and Skip if Condition Satisfied 2.70 (2.92) 



67 


M 


1 


A 


I 


X 


Y 



56 789 



12 13 14 



17 18 



35 



If the bits in AC corresponding to 1 s in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. Change the masked AC bits to Is; the rest of 
AC is unaffected. 



TSO Test Swapped, Ones, but Do Not Skip 

TSO E Test Swapped, Ones, and Skip if All Masked Bits 

Equaled 

TSOA Test Swapped, Ones, but Always Skip 

TSON Test Swapped, Ones, and Skip if Not All Masked 

Bits Equaled 



671 
673 

675 

677 



With these instructions any bit throughout all of memory can be used as a 
program flag, although an ordinary memory location containing flags must 
be moved to an accumulator for testing or modification. The usual pro- 
cedure, since locations 1 - 1 7 are addressable as index registers, is to use AC 
as a register of flags (often addressed symbolically as F). 

Unless one frequently tests flags in both halves of F simultaneously, it is 
generally most convenient to select bits by 1 s right in the address part of the 
instruction word. A given bit selected by a half word mask M is then set by 
one of these: 

TRO F,M TLO F,M 

and tested and cleared by one of these: 

TRZE F,M TRZN F,M TLZE T?,M TLZN F,M 

Suppose we wish to skip if both bits 34 and 35 are 1 in location L. The 
following suffices. 

SETCM F,L 
TRNE F,3 

We can refer to a flag in a given bit position within a word as flag X, where X 
is a binary number containing a single 1 in the same bit position as the flag. 
This sequence determines whether flags X and Y in the right half of accumu- 
lator F are both on: 



2-54 



CENTRAL PROCESSOR 



2.9 



TRC F, X + Y ;Complement flags X and Y 

TRCE F,X+Y ;Test both and restore original states 

;Do this if not both on 
;Skip to here if both on 



2.9 PROGRAM CONTROL 



As no-ops, code 247 takes 
1.50 (1.61) MS, 257 takes 
1.36 (1.47) MS. 



Note that nothing is stored in 
bits 13-17, so when the PC 
word is addressed indirectly it 
can produce neither indexing 
nor further indirect address- 
ing. 



The program control class of instructions includes the unimplemented user 
operations [discussed in the next section] and the arithmetic and logical test 
instructions. Some instructions in this class are no-ops, as are a few of the 
instructions for performing logical operations. The most commonly used 
no-op is JFCL, which is discussed below. No-ops among the instructions 
previously discussed are SETA, SETAI, SETMM, CAI, CAM, JUMP, TRN, 
TLN, TON, TSN. Of these, SETA, SETAI, CAI, JUMP, TRN and TLN do 
not use the calculated effective address to reference memory. Hence in these 
instructions one can store any information in bits 18-35 without fear of 
attempting to address a location outside a user block or in a memory that 
does not exist. The unassigned instruction codes 247 and 257 are used for 
instructions installed specially for a particular system. They execute as 
no-ops when run on a computer that contains no special hardware for them, 
but for program compatibility it is advised that they not be used regularly as 
no-ops. 

The present section treats all program control instructions other than 
those mentioned above and in-out instructions that test input conditions 
[2.12] . All but one of these are jumps, although the exception causes the 
processor to execute an instruction at an arbitrary location and may there- 
fore be regarded as a jump with an immediate and automatic return. Also, 
all but two of the jumps are unconditional; one exception tests various flags, 
the other tests an accumulator. 

Several of the jump instructions save the current contents of the program 
counter PC in the right half of an accumulator or memory location and save 
the states of various flags in the left half. The left bit positions that receive 
information are listed below; all other left bit positions are cleared. An X in 
a mnemonic indicates any letter (or none) that may appear in the given 
position to specify the mode, eg ADDA' comprises ADD, ADDI, ADDM, 
ADDB. 

Bit Meaning of a 1 in the Bit 

Overflow any of the following has occurred: 

A single instruction has set one of the carry flags (bits 1 and 2) 
without setting the other. 

An ASH or ASHC has left shifted a 1 out of bit 1 in a positive 
number or a out in a negative number. 

An MULJf has multiplied -2 35 by itself (product 2 70 ). 



An IMULJf has multiplied two numbers with product 
<-2 35 . 



3S 



or 



2.9 



PROGRAM CONTROL 



2-55 



Floating Overflow has been set (bit 3). 
No Divide has been set (bit 1 2). 

Carry if set without Carry 1 (bit 2) being set, causes Overflow to 
be set and indicates that one of the following has occurred: 

An ADDA' has added two negative numbers with sum < -2 3S . 

An SUBA' has subtracted a positive number from a negative num- 
ber with difference < -2 3S . 

An SO3X or SOSX has decremented -2 3S . 
An MOVNAf or MOVMJT has negated -2 35 . 

But if set with Cany 1, indicates that one of these nonoverflow 
events has occurred: 

In an ADDA' both summands were negative, or their signs differed 
and their magnitudes were equal or the positive one was the 
greater in magnitude. 

In an SUBA' the signs of the operands were the same and AC was 
the greater or the two were equal, or the signs of the operands 
differed and AC was negative. 

An AOJA' or AOSA" has incremented - 1 . 

An SOW or SOSAf has decremented a nonzero number other than 

_ 2 35 

An MOVNAf has negated zero. 

Carry 1 if set without Carry (bit 1) being set, causes Overflow to 
be set and indicates that one of the following has occurred: 

An ADDA' has added two positive numbers with sum > 2 35 . 

An SUBAf has subtracted a negative number from a positive num- 
ber with difference > 2 3S . 

An AOJA' or AOSA' has incremented 2 35 - 1 . 

But if set with Carry 0, indicates that one of the nonoverflow events 
listed under Carry has occurred. 

Floating Overflow - any of the following has set Overflow: 

In a floating point instruction other than DFN, the exponent of 
the result was > 127. 

Floating Underflow (bit 1 1) has been set. 

No Divide (bit 12) has been set in an FDVAf or FDVRA'. 

Byte Interrupt the processor is in a priority interrupt that inter- 
rupted a byte instruction after the processing of the pointer but 
before the processing of the byte. Hence if an ILDB or IDPB was 
interrupted, the pointer now points not to the last byte, but rather 
to the byte that should be handled upon the return to the inter- 
rupted program [2.13]. 

User the processor is in user mode [ 2.15] . 



Remember [2.5], overflow 
is determined directly from 
the carries, not from the 
flags. The carry flags give 
meaningful information only 
if no more than one instruc- 
tion that can set them occurs 
between clearing and reading 
them. 



2-56 



CENTRAL PROCESSOR 



2.9 



If normalized operands are 
used, only a zero divisor can 
cause floating division to fail. 



6 User In-out even if the processor is in user mode, the restrictions 

on user instructions do not apply [2.15]. 

11 Floating Underflow -- in a floating point instruction other than 
DFN, the exponent of the result was < -128 and Overflow and 
Floating Overflow have been set. 

12 No Divide any of the following has set Overflow: 

In a DIVX the dividend was greater than or equal to the divisor. 
In an IDIVX the divisor was zero. 

In an FDVT or FDVRA' the divisor was zero, or the dividend 
fraction was greater than or equal to twice the divisor fraction in 
magnitude; in either case Floating Overflow has been set. 



FLOATING BYTE FLOATING 


OVERFLOW OVERFLOW INTERRUPT UNDERFLOW 


III 1 


1 


CARRY 



CARRY 
1 


1 


/ 


USER 


USER 
IN-OUT 










/ 


NO 
DIVIDE 

















\ 2 


345 


678 


9 10 U 


12 13 14 


15 16 17 



FLAG FORMAT, LEFT HALF OF PC WORD 



The total time required is 
that listed plus the time for 
the instruction executed. If E 
addresses a fast memory loca- 
tion, the instruction executed 
takes .34 /is less than the time 
listed for it. 



The A portion of this instruc- 
tion is ignored. 



XCT 



Execute 



1.36 (1.47) 



256 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Execute the contents of location E as an instruction. Any instruction may 
be executed, including another XCT. If an XCT executes a skip instruction, 
the skip is relative to the location of the XCT (the first XCT if there are 
several in a chain). If an XCT executes a jump, program flow is altered as 
specified by the jump (no matter how many XCTs precede a jump instruc- 
tion, when PC is saved it contains an address one greater than the location of 
the first XCT in the chain). 



N is the number of leading Os. 



JFFO 



Jump if Find First One 



2.19(2.30)4- .20 (TV mod 18) 



243 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



If AC contains zero, clear AC A + l and go on to the next instruction in 
sequence. 

If AC is not zero, count the number of leading Os in it (Os to the left of 
the leftmost 1), and place the count in AC A + \. Take the next instruction 



2.9 



PROGRAM CONTROL 



2-57 



from location E and continue sequential operation from there. 

In either case AC is unaffected, the original contents of AC ^4 + 1 are lost. 



Note that when AC is nega- 
tive, the second accumulator 
is cleared, just as it would be 
if AC were zero. 



JFCL 



Jump on Flag and Clear 



1.36 (1.47) jus 



255 


F 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



If any flag specified by F is set, clear it and take the next instruction from 
location E, continuing sequential operation from there. Bits 9-12 are pro- 
grammed as follows. 



Bit 

9 
10 
11 
12 



Flag Selected by a 1 

Overflow 
Carry 
Carry 1 
Floating Overflow 



To select one or a combination of these flags (which are among those des- 
cribed above) the programmer can specify the equivalent of an AC address 
that places Is in the appropriate bits, but MACRO recognizes mnemonics for 
some of the 13-bit instruction codes (bits 0-12). 



JFCL 

JOV 

JCRYO 

JCRY1 

JCRY 

JFOV 



JFCL 0, 

JFCL 10, 

JFCL 4, 

JFCL 2, 

JFCL 6, 

JFCL 1, 



No-op 25500 

Jump on Overflow 25540 

Jump on Carry 25520 

Jump on Carry 1 25510 

Jump on Carry or 1 25530 

Jump on Floating Overflow 25504 



This instruction can be used 
simply to clear the selected 
flags by having the jump ad- 
dress point to the next con- 
secutive location, as in 

JFCL 17..+ 1 

which clears all four flags 
without disrupting the nor- 
mal program sequence. A 
JFCL that selects no flag is 
the fastest no-op as it neither 
fetches nor stores an operand, 
and bits 18-35 of the instruc- 
tion word can be used to 
store information. 



JSR 



Jump to Subroutine 



2.21 (2.43) jus 



264 


A 


I 


X 


Y 



89 



12 1314 



17 18 



35 



Place the current contents of the flags (as described above) in the left half of 
location E and the contents of PC in the right half (at this time PC contains 
an address one greater than the location of the JSR instruction). Take the 
next instruction from location E + 1 and continue sequential operation from 
there. The flags are unaffected except Byte Interrupt, which is cleared. 

If this instruction is executed as a result of a priority interrupt or in un- 
relocated 41 or 61 while the processor is in user mode, bit 5 of the PC word 
stored is 1 and the processor leaves user mode. 



Interleaving memories saves 
.47 (.36) /as. 



The A portion of this instruc- 
tion is ignored. 



2-58 



CENTRAL PROCESSOR 



2.9 



JSP 



Jump and Save PC 



1. 36 (1.47) /us 



265 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Place the current contents of the flags (as described above) in AC left and 
the contents of PC in AC right (at this time PC contains an address one 
greater than the location of the JSP instruction). Take the next instruction 
from location E and continue sequential operation from there. The flags 
are unaffected except Byte Interrupt, which is cleared. 

If this instruction is executed as a result of a priority interrupt or in un- 
relocated 41 or 61 while the processor is in user mode, bit 5 of the PC word 
stored is 1 and the processor leaves user mode. 



JRST 



Jump and Restore 



1.36 (1.47) 



This is identical to UUO trap- 
ping [2.10]. 



MA actually displays the 
address of the location that 
would have been executed 
next had the JRST been re- 
placed by a no-op. So except 
for a JRST in a priority 
interrupt, MA points to the 
location one beyond that 
containing the instruction 
that caused the halt. This 
instruction is ordinarily the 
JRST or perhaps an XCT, but 
could even be a UUO. 



254 


F 


I 


X 


Y 



89 



12 13 14 



1718 



35 



Perform the functions specified by F, then take the next instruction from 
location E and continue sequential operation from there. Bits 9-12 are 
programmed as follows. 

Bit Function Produced by a 1 

9 Restore the channel on which the highest priority interrupt is cur- 
rently being held [2.13]. 

Unless the User In-out flag is set, this function cannot be executed 
in a user program. Instead of restoring the channel, it stores its own 
instruction code, F and effective address E in bits 0-8, 9-12 and 
18-35 respectively of unrelocated location 40 (clearing bits 13-17), 
and then executes the instruction contained in location 4 1 , which is 
under control of the monitor [2.15]. 

1 Halt the processor. When it stops, the MA lights on the console dis- 
play an address one greater than that of the location containing the 
instruction that caused the halt, and PC displays the jump address 
(the location from which the next instruction will be taken if the 
operator causes the processor to resume operation without changing 
PC). 

Unless the User In-out flag is set, this function cannot be executed 
in a user program. Instead of halting the processor, it stores its 
own instruction code, F and effective address in Bits 0-8, 9-12 
and 18-35 respectively of unrelocated location 40 (clearing bits 
13-17), and then executes the instruction contained in location 41, 
which is under control of the monitor [2.15]. 

1 1 Restore the flags listed above from the left half of the word in the 
last location referenced in the effective address calculation. Hence 
to restore flags requires that the JRST instruction use indexing or 



2.9 



PROGRAM CONTROL 



2-59 



12 



indirect addressing. 

Restoration of all but the user flags is directly according to the 
contents of the corresponding bits as given above: a flag is set by a 1 
in the bit, cleared by a 0. A 1 in bit 5 sets User but a has no effect, 
so the Monitor can restart a user program by restoring flags but the 
user cannot leave user mode by this method. A in bit 6 clears User 
In-out, but a 1 sets it only if the JRST is being executed by the 
Monitor, ie if User is clear. 

Enter user mode. The user program starts at relocated location E. 



To produce one or a combination of these functions the programmer can 
specify the equivalent of an AC address that places Is in the appropriate bits, 
but MACRO recognizes mnemonics for the most important 13-bit instruction 
codes (bits 0-1 2). 



JRST 

HALT 
JRSTF 

JEN 



JRST 0, 

JRST 10, 

JRST 4, 

JRST 2, 

JRST 1, 

JRST 12, 



Jump 

Jump and Restore 
Interrupt Channel 

Halt 

Jump and Restore Flags 
Jump to User Program 
Jump and Enable 



25400 
25440 

25420 
25410 
25404 
25450 



In a JRSTF or JEN the flags are restored from bits 0- 1 2 of the final word 
retrieved in the effective address calculation; hence any JRST with a 1 in bit 
11 must use indirect addressing or indexing, which takes extra time. If the 
PC word was stored in AC (as in a JSP), a common procedure is to use AC to 
index a zero address (eg, JRSTF (AC)), so its right half becomes the effec- 
tive Gump) address. If the PC word was stored in core (as in -a JSR), one 
must address it indirectly (remember, bits 13-17 of the PC word are clear, 
so again its right half is the effective address). A JRSTF (AC) takes 1.64 
(1.75) jus, a JRSTF PCWORD takes 2.34 (2.56) MS. 

CAUTION 

Giving a JRSTF or JEN without indexing or 
indirect addressing restores the flags from the 
instruction code itself. 

If this instruction is executed as a result of a priority interrupt or in 
unrelocated 41 or 61 while the processor is in user mode, bit 5 of the PC_ 
word stored is 1 and the processor leaves user mode. 



JFCL is the only jump that can test any of the flags directly. In fact it is 
the only basic program control instruction that can do so several of the 
flags can be tested as processor conditions by in-out instructions, but these 
are ordinarily illegal in user programs anyway. But JFCL can test only four 



By manipulating the contents 
of the left half word used to 
restore the flags, the program- 
mer can set them up in any 
desired way except that a 
user program cannot clear 
User or set User In-out. jet- 
ting Byte Interrupt prevem^ 
incrementing in the next 
ILDB or IDPB provided there, 
is no intervening JSR. JSP or 
PUSHJ. 



JEN completes an interrupt 
by restoring the channel and 
restoring the flags for the 
interrupted program. 






2-60 CENTRAL PROCESSOR 2.9 

of the flags, and it saves no information for a subsequent return from a sub- 
routine. Hence it serves as a branch point for entry into either one of two 
main paths, which may or may not have a later point in common. Eg, it may 
test the carry flags simply to take appropriate action in a double precision 
fixed point routine. 

JSR and JSP are regularly used to call subroutines. They are uncondi- 
tional, but the execution of such an instruction can be the result of a 
decision made by any conditional skip or jump. In the case of the flags, a 
basic overflow test and subroutine call can be made as follows. 

JOV .+2 
The fastest skip is CAIA. JRST . +2 ; Faster than skipping 

JSR OVRFLO ; Jump over this if Overflow clear 



If we wish to go to the DIVERR routine when No Divide is set, we must first 
read the flags into a test accumulator T and then use a test instruction. 

JSP T, . + 1 ;Store flags but continue in sequence 

TLNE T,40 ;40 left selects bit 1 2 

JSR DIVERR ;Skip this if No Divide clear 



A subroutine called by a JSR must have its entry point reserved for the PC 
word. Hence it is nonreentrant: the JSR modifies memory so the subroutine 
cannot be shared with other programs. The JSP requires an accumulator, 
but it is faster and is convenient for argument passing. To return from a 
JSR-called subroutine one usually addresses the PC word indirectly, return- 
ing to the location following the JSR. But there are two ways to get back 
from a JSP. We can address the PC word indirectly with a JRST @AC (or 
JRSTF @AC if the flags must be restored), but we can also get it by 
addressing AC as an index register: JRST (AC). By using the second return 
method we can place N words of data for the subroutine immediately after 
the call, and return to the location following the data by giving a 
JRST 7V(AC). 

Suppose we wish to call a print subroutine and supply the words from 
which the characters are to be taken. Our main program would contain the 
following: 

JSP T, PRINT ;Put PC word in accumulator T 

;Text inserted here by ASCIZ pseudo- 

i instruction, which automatically 

;places a zero (null) character at the 
;end 
;Next instruction here 

The subroutine can use T as a byte pointer which already addresses the first 
word of data. For the print routine, characters are loaded into another 
accumulator CH. 



2.9 
PRINT: 



HRLI 
ILDB 
JUMPE 



T,440700 

CH,T 

CH,1(T) 



JRST PRINT+1 



PROGRAM CONTROL 

Initialize left half of pointer 
;Increment pointer and load byte 
;Upon reaching zero character return 
;to one beyond last data word 
;Print routine 

;Get next character 



2-61 



JSA 



Jump and Save AC 



2.82 (2.93) jus 



266 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Place AC in location E, the effective address E in AC left, and the contents 
of PC in AC right (at this time PC contains an address one greater than the 
location of the JSA instruction). Take the next instruction from location 
E + 1 and continue sequential operation from there. The original contents 
of E are lost. 

If this instruction is executed as a result of a priority interrupt or in 
unrelocated 41 or 61 while the processor is in user mode, bit 5 of the PC 
word stored is 1 and the processor leaves user mode. 



JRA 



Jump and Restore AC 



2.92 (3. 14) /us 



267 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Place the contents of the location addressed by AC left into AC. Take the 
next instruction from location E and continue sequential operation from 
there. 



Interleaving 
.47 (.36) jus. 



memories saves 



A JSA combines advantages of the JSR and JSP. JSA does modify 
memory, but it saves PC in an accumulator without losing its previous 
contents (at a cost of not saving the flags). It is thus convenient for multiple- 
entry subroutines. In a subroutine called by a JSR, the returning JRST must 
refer to the (single) entry point. Since a JRA can retrieve the original PC by 
addressing AC as an index register, it is independent of any entry point 
without tying up an accumulator to the extent a JSP would. 

The accumulator contents saved by a JSA are restored by a JRA paired 
with it despite intervening JSA-JRA pairs. Hence these instructions are 
especially useful for nesting subroutines, as shown by this example. 



In FORTRAN IV, a CALL 
statement uses JSA with AC 
16. 



2-62 



CENTRAL PROCESSOR 



2.9 



SI: 



JSA 







JSA 



17, SI 



17,82 



S2: 



JRA 17, (17) 





;Main program 

;Call to first subroutine (A) 

;First subroutine starts here 
;Call to second subroutine (B) 

; Return to A + 1 in main program 
;Second subroutine starts here 



JSA 



S3: 



.7,83 



;Call to third subroutine (C) 



JRA 17, (17) ;Return to B + 1 in first subroutine 

;Third subroutine starts here 



JRA 



;Return to C+ 1 in second subroutine 



To call the next deeper subroutine at any level, a JSA places E and PC in the 
left and right of AC 17, saves the previous contents of AC 17 in (the first 
subroutine location), and jumps to E + 1 . To return to the next higher level, 
a JRA restores the previous contents of AC 17 from the location addressed 
by AC 17 left (the first subroutine location) and jumps to the location 
addressed by AC 17 right (the location following the JSA in the higher sub- 
routine). If N lines of data for the next subroutine follow a JSA, the return 
to the location following the data is made by giving a JRA 17,Af(17). 



Keeping instructions and the 
pushdown list in different 
memories saves .47 (.36) /us. 



PUSHJ 



Push Down and Jump 



3.00 (3. 11) 



260 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC to increment both halves by one and place the result 
back in AC. If the addition causes the count in AC left to reach zero, set the 
Pushdown Overflow flag. Then place the current contents of the flags (as 
described above) in the left half of the location now addressed by AC right 
and the contents of PC in the right half of that location (at this time PC 
contains an address one greater than the location of the PUSHJ instruction). 
Take the next instruction from location E and continue sequential operation 
from there. 

The flags are unaffected except Byte Interrupt, which is cleared. The 
original contents of the location added to the list are lost. 

If this instruction is executed as a result of a priority interrupt or in 
unrelocated 41 or 61 while the processor is in user mode, bit 5 of the PC 
word stored is 1 and the processor leaves user mode. 



2.9 
POPJ 



PROGRAM CONTROL 



Pop Up and Jump 



2.96 (3. 18) 



263 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Subtract 1 00000 1 8 from AC to decrement both halves by one and place the 
result back in AC. If the subtraction causes the count in AC left to reach -1, 
set the Pushdown Overflow flag. Take the next instruction from the location 
addressed by the right half of the location that was addressed by AC right 
prior to the decrementing, and continue sequential operation from there. 



2-63 



The effective address E is 
ignored. 



The address of the top item in the pushdown list is kept in the right half 
of the pointer in AC, and the program can keep a control count in the left 
half. The incrementing and decrementing of both halves of AC simulta- 
neously is effected by adding and subtracting 1 00000 1 8 . Hence a count of 
-2 in AC left is increased to zero if 2 18 - 1 is incremented in AC right, and 
conversely, 1 in AC left is decreased to -1 if zero is decremented in AC 
right. 

Since the pushdown list is independent of the subroutine called, PUSHJ- 
POPJ can be used like JSA-JRA for multiple entries. Moreover, ordering by 
level is inherent in the structure of a pushdown list [2.2], so paired 
PUSHJ-POPJ instructions are excellent for nesting subroutines: there can be 
any number of subroutines at any level, each with more subroutines nested 
within it. Recursive subroutines are also possible. 

Unlike JSA-JRA, the pushdown instructions tie up an accumulator, but 
the usual procedure is to keep both data and jump addresses in a single list so 
only one AC is required for the most complex pushdown operations. The 
programmer must keep track of whether a given entry in the list is data or 
a PC word; in other words, every item inserted by a PUSH should be 
removed by a POP, and every PUSHJ should be matched bv a PQPJ. If flag 
restoration is desired, the returning 



POPJ 

can be replaced by 

POP 
JRSTF 



P, 



P,AC 

(AC) 



which requires another accumulator, ^f the flags are not important, data 
may be stored in the left halves of the PC words in the stack, redlining the 
required pushdown depth. 

By using the Pushdown Overflow flag and a control count in AC left, the 
programmer can set a limit to the size of the list by starting the count 
negative, or he can prevent the program from extracting more items than 
there are in the list by starting the count at zero, but he cannot do both at 
once. If only jump addresses are kept in the list, the first procedure limits 
the depth of nesting. A technique to catch extra POPJs is to put a PC word 
addressing an error routine at the bottom of the list. 



2-64 



An unimplemented user oper- 
ation is usually referred to as 
a UUO, but this mnemonic 
means nothing to the assem- 
bler. UUOs are also some- 
times called "programmed 
operators". 



CENTRAL PROCESSOR 

2.10 UNIMPLEMENTED OPERATIONS 



2.10 



Many of the codes not assigned as specific instructions are executed as 
unimplemented user operations, wherein the word given as an instruction is 
trapped and must be interpreted by a routine included for this purpose by 
the programmer. In time sharing, however, half of the codes are set aside for 
user communication with the Monitor and are interpreted by it. Instructions 
that are illegal in user mode also trap in this manner. 



The total time required is 
that listed plus the time for 
the instruction in location 41. 
Interleaving memories and 
1 saves .47 (.36) /LIS. 



Unimplemented User Operation 



2.33 (2.44) 



000-077 


A 


1 


X 


Y 



89 



12 13 14 



17 18 



35 



Store the instruction code, A and the effective address E in bits 0-8, 9-12 
and 18-35 respectively of location 40; clear bits 13-17. Execute the 
instruction contained in location 41. The original contents of location 40 
are lost. 

All of these codes are equivalent when they occur in the Monitor or when 
time sharing is not in effect. But when a UUO appears in a user program, a 
code in the range nni -rm ^^ rpio^atH l^^tirmQ 4n and 41 (ig 40 and 41 



in the jjser's block) and is thus entirely a part of and under control of the 
user program. A code in the range 040-077 on the other hand uses 
unrelocated 40 and 41, and the instruction in the latter location is under 
control of the Monitor; these codes are thus specifically for user communica- 
tion with the Monitor, which interprets them (refer to the Monitor manual 
for the meanings of the various codes). The code 000 executes in the same 
way as 040-077 but is not a standard communication code: it is included so 
that control returns to the Monitor should a user program wipe itself out. 

For a second processor connected to the same memory, the UUO trap is 
locations 140-141 instead of 40-41. 



The unimplemented operations also include the reserved (unassigned) 
instruction codes 100-127, which execute like the Monitor-calling UUOs 
but use unrelocated 60-61 (160-161 for a second processor); thus the 
Monitor steps in when a user gives an incorrect code. The codes 130-177, 
which are the floating point and byte manipulation instructions, are equiva- 
lent to the unassigned codes if unimplemented, ie if the optional hardware 
for them is not included* In this case all codes 100-177 trap to unrelocated 
60-61 . In general it is assumed that if software is available for floating point 
and byte manipulation, the Monitor is responsible for calling the appropriate 
routines. 



2.11 PROGRAMMING EXAMPLES 2-65 

2.11 PROGRAMMING EXAMPLES 

Before continuing to input-output and related subjects, let us consider som 
simple programs that demonstrate the use of a variety of the instruction 
described thus far. 

Suppose we wish to count the number of Is in a word. We could of 
course check every bit in the word. But there is a quicker way if we remem- 
ber that in any word and its twos complement the rightmost 1 is in the same 
position, both words are all Os to the right of this 1, and no corresponding 
bits are the same to the left (the parts of both words at the left of the right- 
most 1 are complements). Hence using the negative of a word as a mask for 
the word in a test instruction selects only the rightmost 1 for modification. 
The example uses three accumulators: the word being tested (which is lost) 
is in T, the count is kept in CNT, and the mask created in each step is stored 
in TEMP. 

MOVEI CNT,0 ;ClearCNT 

MOVN TEMP,T ;Make mask to select rightmost 1 

TDZE T,TEMP ;Clear rightmost 1 in T 

AOJA CNT,. -2 ;Increase count and jump back 

;Skip to here if no Is left in T 

CNT is increased by one every time a 1 is deleted from T. After all Is have 
been removed, the TDZE skips. 

In the standard algorithm for converting a number TV to its equivalent in 
base b, one performs the series of divisions 

N/b qi + rjb r l < b 

q\lb q 2 + r 2 /b r 2 < b 

Qi/b = q 3 + r 3 /b r 3 < b 



q n -i/b = Q + r n /b r n <b 

The number in base b is then r n . . . r 3 r 2 r, . Eg the octal equivalent of 61 
decimal is 75: 

61/8 = 7 + 5/8 
7/8 = + 7/8 

The following decimal print routine converts a 36-bit positive integer in 
accumulator T to decimal and types it out. The contents of T and T+ 1 are 
destroyed. The routine is called by a PUSHJ P, DECPNT where P is the 
pushdown pointer. 

DECPNT: IDIVI T,12 ;12 8 =10, 

PUSH P,T+1 ;Save remainder 

SKIPE T ;A11 digits formed? 

PUSHJ P, DECPNT ;No, compute next one 



2-66 CENTRAL PROCESSOR 2.11 

DECPN1: POP P,T ;Yes, take out in opposite order 

ADDI T, 60 ;Convert to ASCII (60 is code for 0) 

JRST TTYOUT ;Type out 

This routine repeats the division until it produces a zero quotient. Hence it 
suppresses leading zeros, but since it is executed at least once it outputs one 
"0" if the number is zero. The TTYOUT routine returns with a POPJ P, to 
DECPN1 until all digits are typed, then to the calling program. 

Space can be saved in the pushdown stack by storing the computed digits 
in the left halves of the locations that contain the jump addresses. This is 
accomplished in the decimal print routine by making the following substi- 
tutions. 

PUSH P,T+1 -> HRLM T+1,(P) 
POP P,T -> HLRZ T,(P) 

The routine can handle a 36-bit unsigned integer if the IDIVI T, 12 is 
replaced by 

MACRO interprets a number LSHC T,~tD35 ;Shift right 35 bits into T+l 

following tD as decimal. LSH T+1,-1 ; Vacate the T+ 1 sign bit 

DIVI T, 12 ; Divide double length integer by 10 

Many data processing situations involve searching for information in tables 
and lists of all kinds. Suppose we wish to find a particular item in a table 
beginning at location TAB and containing N items. Accumulator T contains 
the item. The right half of A is used to index through the table, while the 
left half keeps a control count to signal when a search is unsuccessful. 

MOVSI A,-N ;Put -N, in A 

CAMN T,TAB(A) ;Skip if current item not the one 
JRST FOUND ;Item found 

AOBJN A, .-2 ;Try next item until left count = 

;Item not in list 

The location of the item (if found) is indicated by the number in the right 
half of A (its address is that quantity plus TAB). A slightly different pro- 
cedure would be 

HRLZI A..-N 

CAME T,TAB(A) ;Skip if current item is the one 

AOBJN A, . - 1 

JUMPL A, FOUND ;Jump if left count < 

. . . ;Item not found 

Locations used for a list can be scattered throughout memory if data is 
kept in the left half of each location and the right half addresses the next 
location in the list. The final location is indicated by a zero right half. The 
following routine finds the last half word item in the list. It is entered at 
FIND with the first location in the list addressed by the right half of 
accumulator T. At the end the final item is in T right. 



2.11 



PROGRAMMING EXAMPLES 



2-67 



MOVE T,(T) 

FIND: TRNE 1,111111 

JRST .-2 

HLRZS T 



;Move next item to T 
; Skip if AC right = 

;Move final item to right 



The following counts the length of the list in accumulator CNT. 

MOVEI CNT,0 ;ClearCNT 

JUMPE T,OUT ;Jump out if T contains 

HRRZ T,(T) ;Get next address 

AOJA CNT,. -2 ;Count and go back 



I 



A 

rVt? 



-A 
AH 



Ad 



Double Precision Floating Point. The following are straightforward rou- 
tines for handling double precision floating point arithmetic [ 2.6 describes 
the floating point instructions] . 



DFAD: 



DFSB: 



DFMP: 



UFA 


A+1,M+1 


FADL 


A,M 


UFA 


A+l, A+2 


FADL 


A,A+2 


POPJ 


P, 


DFN 


A,A+1 


PUSHJ 


P,DFAD 


DFN 


A, A+l 


POPJ 


P, 


MOVEM 


A,A+2 


FMPR 


A+2,M+1 


FMPR 


A+1,M 


UFA 


A+l, A+2 


FMPL 


A,M 


UFA 


A+l, A+2 


FADL 


A,A+2 


POPJ 


P, 



;Sum of low parts to A+2 
;Sum of high parts to A, A+ 1 
;Add low part of high sum to A+2 
;Add low sum to high sum 

;Negate double length operand 
;Call double floating add 
;-(M - AC) = AC - M 

;Copy high AC operand in A+2 

;One cross product to A+2 

;Other to A+ 1 

;Add cross products into A+2 

;High product to A, A+l 

;Add low part to cross sum in A+2 

;Add low sum to high part of product 



A 
A+l 



A double precision division is of the form 

A a + cX2" 27 

B b + dX2~ 21 



Using the relationship 



Alb = q + 



where q and r are the quotient and remainder produced by FDVL, the 
following routine computes a double length quotient by the algorithm 



A ^ ( 
B 



which gives a result correct to the next-to-last bit in the low order half. 



2-68 



CENTRAL PROCESSOR 



12.12 



DFDV: 



FDVL 


A,M 


MOVN 


A+2,A 


FMPR 


A+2,M+1 


UFA 


A+l.A+2 


FDVR 


A+2,M 


FADL 


A,A+2 


POPJ 


P, 



;Get high part of quotient 

;Copy negative of quotient in A+2 

;Multiply by low part of divisor 

;Add remainder 

;Divide sum by high part of divisor 

;Add result to original quotient 



2.12 INPUT-OUTPUT 



Times are given for IO in- 
structions when they occur 
alone. When two 10 instruc- 
tions are given consecutively, 
the second often takes longer 
(refer to the timing chart in 
Appendix C for details). 



This is identical to UUO trap- 
ping [2.10]. 



The input-output instructions govern all transfers of data to and from the 
peripheral equipment, and also perform many operations within the proc- 
essor. An instruction in the in-out class is designated by 1 1 1 in bits 0-2, ie 
its left octal digit is 7. Bits 3-9 address the device that is to respond to the 
instruction. The format thus allows for 128 codes, two of which, 000 and 
004 respectively, address the processor and priority interrupt, and are used 
for the console and time share hardware as well. A chart 'n Appendix A 
lists all devices for which codes have been assigned, and gives their 
mnemonics and DEC option numbers. 

Bits 13-35 are the same as in all other instructions: they are the /, X, and 
Y parts, which are used to calculate an effective address, set of conditions, 
or mask to be used in the execution of the instruction. The remaining bits, 
10-12, select one of the following eight IO instructions. 

NOTE 

All instructions described in the remainder of this manual are in-out 
instructions, which cannot be executed in user programs unless the 
User In-out flag is set. If an in-out instruction appears in a user pro- 
gram while User In-out is clear, it does not perform the functions given 
for it in the instruction description. Instead it stores its own instruc- 
tion and device codes in bits 0- 1 2 and its effective address E in bits 
18-35 of unrelocated location 40 (clearing bits 13-17), and then 
executes the instruction contained in location 41. The latter location 
is under control of the Monitor [2.15]. 

This user restriction will not be mentioned in the instruction descrip- 
tions, as it applies to all instructions from this point on. 



E will always be regarded as 
being bits 18-35, even though 
it is actually placed on both 
halves of the bus and many 
devices receive the informa- 
tion from the left half. 



CONO 



23 



Conditions Out 



3.90 (4.01) 



7 


D 


20 


/ 


X 


Y 



910 121314 



17 18 



35 



Set up device D with the effective initial conditions E. The number of con- 
dition bits in E that are actually used depends on the device. 



MAY 1968 



2.12 
COM 



INPUT-OUTPUT 



Conditions In 



4.87 (4.98) jus 



7 


D 


24 


I 


X 


Y 



9 10 12 13 14 



17 18 



35 



Read the input conditions from device D and store them in location E. The 
number of condition bits stored depends on the device; the remaining bits 
in location E are cleared. 



DATAO 



Data Out 



4.75 (4.97) /us 



7 


D 


1 4 ] 


/ 


X 


Y 



2 3 



9 10 12 13 14 



17 18 



35 



Send the contents of location E to the data buffer in device D, and perform 
whatever control operations are appropriate to the device. 

The amount of data actually accepted by the device depends on the size 
of its buffer, its mode of operation, etc. The original contents of location E 
are unaffected. 



DATAI 



Data In 



4.87 (4.98) /us 



7 


D 


04 


/ 


X 


Y 



2 3 



9 10 12 13 14 



17 18 



35 



Move the contents of the data buffer in device D to location E, and perform 
whatever control operations are appropriate to the device. 

The number of data bits stored depends on the size of the device buffer, 
its mode of operation, etc. Bits in location E that do not receive data are 
cleared. 



2-69 

Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /us. Bringing 
conditions into fast memory 
saves .46 (.35) /us. 



Taking the output word from 
fast memory saves .34 /us. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /us. Placing the 
input data in fast memory 
saves .46 (.35) pis. 



CONSZ 



23 



Conditions In and Skip if Zero 



4.11 (4. 22) /us 



7 


D 


30 


/ 


X 


Y 



9 10 12 13 14 



17 18 



35 



Test the input conditions from device D against the effective mask E. If all 
condition bits selected by Is in E are Os, skip the next instruction in 
sequence. 

If the device supplies more than 18 condition bits, only the right 18 are 
tested. 



2-70 



CONSO 



CENTRAL PROCESSOR 



Conditions In and Skip if One 



2.12 
4.11 (4.22) jus 



7 


D 


34 


/ 


X 


Y 



23 



9 10 12 13 14 



17 18 



35 



Test the input conditions from device D against the effective mask E. If any 
condition bit selected by a 1 in E is 1 , skip the next instruction in sequence. 
If the device supplies more than 18 condition bits, only the right 18 are 
tested. 



Keeping the pointer in fast 
memory saves .43 (.34) ;us. 



Keeping the pointer in fast 
memory saves .34 /us. Keeping 
the instruction and the data 
block in different memories 
saves .47 (.36) /us. 



A block 10 instruction is 
effectively a whole in-out 
data handling subroutine. It 
keeps track of the block loca- 
tion, transfers each data 
word, and determines when 
the block is finished. 

Initially the left half of the 
pointer contains the negative 
of the number of words in 
the block, the right half con- 
tains an address one less than 
that of the first word irj, the 
block. 



A BLKO 



Block Out 



6.49 (6.71) 




7 


D 


10 


I\ X 


Y 


23 910 121314 1718 35 


BLKI Block In 6.49 (6.71) /us 


7 


D 


00 


I X 


Y 



23 



910 121314 



17 18 



35 



Add 1 000001 8 to a pointer in location E to increment both halves by one, 
and place the result back in E. Then perform a data IO instruction in the 
same direction as the block IO instruction, using the right half of the incre- 
mented pointer as the effective address. If the given instruction is a BLKO, 
perform a DATAO; if a BLKI, perform a DATAI. 

The remaining actions taken by this instruction depend on whether it is 
executed as a priority interrupt instruction [ 2.13] . 

4 Not as an Interrupt Instruction. If the addition has caused the count in 
the left half of the pointer to reach zero, execute the next instruction in 
sequence. Otherwise skip the next instruction. 

4 As an Interrupt Instruction. If the addition has caused the count in the 
left half of the pointer to reach zero, execute the instruction in the second 
interrupt location for the channel. Otherwise dismiss the interrupt and 
return to the interrupted program. 



The above eight instructions differ from one another in their total effect, 
but they are not all different with respect to any given device. A BLKO acts 
on a device in exactly the same way as a DATAO the. two differ only in 
counting and other operations carried out within the processor and memory. 
Similarly, no device can distinguish between a BLKI and a DATAI; and a 
device always supplies the same input conditions during a CONI, CONSZ or 
CONSO whether the program tests them or simply stores them. 

Hence the eight instructions may be categorized as of four types, repre- 
sented by the first four instructions described above. Moreover, a complete 
treatment of the programming of any device can be given in terms of these 
four instructions, two of which are for input and two for output. The four 



MAY 1968 



2.12 



INPUT-OUTPUT 



2-71 



exhaust the types of information transfer that occur in the IO system, at 
least three of which are applicable to any given device. Thus all instruction 
descriptions in the rest of this manual will be of the CONO, CONI, DATAO 
and DATAI instructions combined with the various device codes. The dis- 
cussion of each device will present timing information pertinent to device 
operation, but no instruction times will be included as they are identical to 
those given above. 

Every device requires initial conditions; these are sent by a CONO, which 
can supply up to eighteen bits of control information to the device control 
register. The program can determine the status of the device from up to 
thirty-six bits of input conditions that can be read by a CONI (but only the 
right eighteen can be tested by a CONSZ or CONSO). Some input bits 
simply reflect initial conditions sent by a previous CONO ; others are set up 
by output conditions but are subject to subsequent adjustment by the 
device; and still others, such as status levels from a tape transport, have no 
direct connection with output conditions. 

Data is moved in and out in characters of various sizes or in full 36-bit 
words. Each transfer between memory and a device data buffer requires a 
single DATAI or DATAO. Every device has a CONO and CONI, but it may 
have only one data instruction unless it is capable of both input and output. 
Eg, the paper tape reader has only a DATAI, the tape punch has only a 
DATAO, but the teletype has both. (A high speed device, such as a disc file, 
can be connected to the DF10 Data Channel, which in turn is connected 

I directly to memory by a separate memory bus and handles data auto- 
matically. This eliminates the need for the program to give a DATAO or 
DATAI for each transfer.) 

A Typical IO Device. Every device has a 7-bit device selection network, a 
priority interrupt assignment, and at least two flags, Busy and Done, or some 
equivalent. The selection network decodes bits 3-9 of the instruction so 
that only the addressed device responds to signals sent by the processor over 
the in-out bus. To use the device with the priority interrupt, the program 
must assign a channel to it. Then whenever an appropriate event occurs in 
the device, it requests an interrupt on the assigned channel. 

The Busy and Done flags together denote the basic state of the device. 
When both are clear the device is idle. To place the device in operation, a 
CONO or DATAO sets Busy. If the device will be used for output, the pro- 
gram must give a DATAO that sends the first unit of data - a word or char- 
acter depending on how the device handles information. When the device has 
processed a unit of data, it clears Busy and sets Done to indicate that it is 
ready to receive new data for output, or that it has data ready for input. 
In the former case the program would respond with a DATAO to send more 
data; in the latter, with a DATAI to bring in the data that is ready. If an 
interrupt channel has been assigned to the device, the setting of Done signals 
the program by requesting an interrupt; otherwise the program must keep 
testing Done to determine when the device is ready. 

All devices function basically as described above even though the number 
of initial conditions varies considerably. Besides Busy and Done flags, the 
tape reader and punch have a Binary flag that determines the mode of 
operation of the device with respect to the data it processes - alphanumeric 



The word "input" used with- 
out qualification always refers 
to the transfer of data from 
the peripheral equipment into 
the processor; "output" refers 
to the transfer in the opposite 
direction. 



A DATAI that addresses an 
output-only device simply 
clears location E. DATAI PI, 
(code 70044) produces only 
this effect as the priority in- 
terrupt has no data for input. 
On the other hand a DATAO 
that addresses an input-only 
device is a no-op. 

When the device code is 
undefined or the addressed 
device is not in the system, 
a DATAO, CONO or CONSO 
is a no-op, a CONSZ is an 
absolute skip, a DATAI or 
CONI clears location E. 



Busy and Done both set is a 
meaningless situation. 



2-72 



CENTRAL PROCESSOR 



2.1 



Occasionally a device with a 
second code may use a 
DATAI or DATAO to trans- 
mit additional control or 
maintenance information. 



or binary. The teletype has no binary flag, but it has two Busy flags and two 
Done flags - one pair for input, another for output. A complicated device, 
such as magnetic tape, may require two device codes to handle the large 
number of conditions associated with it. Initial conditions for a tape system 
include a transport address and an actual command the tape control is to 
perform; input conditions include error flags and transport status levels. 

Most IO devices involve motion of some sort, usually mechanical (in a 
display only the electron beam moves). With respect to mechanical motion 
there are two types of devices, those that stay in motion and those that do 
not. Magnetic tape is an example of the former type. Here the device 
executes a command (such as read, write, space forward) and the done flag 
indicates when the entire operation is finished. A separate data flag signals 
each time the device is ready for the program to give a DATAI or DATAO, 
but the tape keeps moving until an entire record or file has been processed. 

Paper tape, on the other hand, stops after each transfer, but the program 
need not give a new CONO every time. The reader logic is set up so that a 
DATAI not only reads the data, but also clears Done and sets Busy. Hence 
if the instruction is given within a critical time, the tape moves continuously 
and only two CONOs are required for a whole series of transfers: one to start 
the tape, and one to stop it after the final DATAI. 

Other devices operate in one or the other of these two ways but differ in 
various respects. The tape punch and teletype output are like the reader. 
Teletype input is initiated by the operator striking a key rather than by the 
program. The card reader reads an entire card on a single CONO, with a 
DATAI required for each column. The DECtape stays in motion, and the 
program must give a CONO to stop it or it will go all the way to the end 
zone. 




Readin Mode 

This mode of processor operation provides a means of placing information 
in memory without relying on a program already in memory or loading one 
word at a time manually. Its principal use is to read in a short loader 
program which is then used for loading other information. A loader program 
should ordinarily be used rather than readin mode, as a loader can check the 
validity of the information read. 

Pressing the readin key on the console activates readin mode by starting 
the processor in a special hardware sequence that simulates a DATAI fol- 
lowed by a series of BLKI instructions, all of which address the device whose 
code is selected by the readin device switches on the small panel at the left 
of the paper tape reader. Various devices can be used, and for each there 
are special rules that must be followed. But the readin mode characteristics 
of any particular device are treated in the discussion of the device. Here we 
are concerned only with the general characteristics. 

The information read is a block of data (such as a loader program) pre- 
ceded by a pointer for the BLKI instructions. The left half of the pointer 
contains the negative of the number of words in the block, the right half 
contains an address one less than that of the location that is to receive the 
first word. 



2.13 



PRIORITY INTERRUPT 



2-73 



To read in, the operator must set up the device he is using, set its code 
into the readin device switches, and press the readin key. The processor 
places the device in operation, brings the first word (the pointer) into 
location 0, and then reads the data block, placing the words in the locations 
specified by the pointer. Data can be placed anywhere in memory (including 
fast memory) except in location 0. The operation affects none of memory 
except location and the block area. 

Upon completing the block, the processor halts only if the single instruc- 
tion switch is on. Otherwise it leaves readin mode, and begins normal 
operation by executing the last word in the block as an instruction. 



Console Data Transfers 

Neither the processor nor the priority interrupt system require all four types 
of IO instructions, so the program can make use of their device codes for 
communicating with the console. 



DATAI APR, Data In, Console 



70004 


/ 


X 


Y 



121314 1718 

Read the contents of the console data switches into location E. 



35 



MACRO also recognizes the 
mnemonic RSW (Read 
Switches) as equivalent to 
DATAI APR,. 



DATAO PI, 



Data Out, Console 



70054 


/ 


X 


Y 



12 13 14 



17 18 



35 



Unless the console MI program disable switch is on, display the contents of 
location E in the console memory indicators and turn on the triangular light 
beside the words PROGRAM DATA just above the indicators (turn off the 
light beside MEMORY DATA). 

Once the indicators have been loaded by the program, no address condi- 
tion selected from the console [2.16] can load them until the operator 
turns on the MI program disable switch, executes a key function that ref- 
erences memory, or presses the reset key. 



2.13 PRIORITY INTERRUPT 

Most in-out devices must be serviced infrequently relative to the processor 
speed and only a small amount of processor time is required to service them, 
but they must be serviced within a short time after they request it. Failure 
to service within the specified time (which varies among devices) can often 



2-74 CENTRAL PROCESSOR 2.13 

result in loss of information and certainly results in operating the device 
below its maximum speed. The priority interrupt is designed with these 
considerations in mind, ie the use of interruptions in the current program 
sequence facilitates concurrent operation of the main program and a number 
of peripheral devices. The hardware also allows conditions internal to the 
processor to signal the program by requesting an interrupt. 

Interrupt requests are handled through seven channels arranged in a 
priority chain, with assignment of devices to channels entirely at the discre- 
tion of the programmer. To assign a device to a channel, the program sends 
the number of the channel to the device control register as part of the condi- 
tions given by a CONO (usually bits 33-35). Channels are numbered 1-7, 
with 1 having the highest priority; a zero assignment disconnects the device 
from the interrupt channels altogether. Any number of devices can be 
connected to a single channel, and some can be connected to two channels 
(eg a device may signal that data is ready on one channel, that an error has 
occurred on another). 

Interrupt Requests. When a device requires service it sends an interrupt 
request signal over the in-out bus to its assigned channel in the processor. If 
the channel is on, the processor accepts the request at the next memory 
access unless the processor is either starting an interrupt on any channel or 
holding an interrupt on the same channel. The request signal is a level, so 
it remains on the bus until turned off by the program (CONO, DATAO or 
DATAI). Thus if a request is not accepted because of the conditions given 
above, it will be accepted when those conditions no longer hold. A single 
channel will shut out all others of lower priority if every time its service 
routine dismisses the interrupt, a device assigned to it is already waiting with 
another request. The program can usually trigger a request from a device but 
delay its acceptance by turning on the channel later. 

Starting an Interrupt. After a request is accepted the channel must wait 
for the interrupt to start. No interrupts can be started unless the priority 
interrupt system is active. Furthermore, the processor cannot start an 
interrupt if it is alreadyt holding an interrupt on a channel with priority 
higher than those on which requests have been accepted (in other words if 
the current program is a higher priority interrupt routine). If there is a 
higher priority channel waiting, the processor stops the current program to 
start an interrupt on the waiting channel that has highest priority. The inter- 
rupt starts following the retrieval of an instruction, following the retrieval of 
an address word in an effective address calculation (including the second cal- 
culation using the pointer in a byte instruction), or following a transfer in a 
BLT. When an interrupt starts, PC points to the interrupted instruction, so 
that a correct return can later be made to the interrupted program. 

Two memory locations are assigned to each channel: unrelocated locations 

Interrupt locations for a sec- 40 + 2N and 4 1 + 27V, where TV is the channel number. Channel 1 uses loca- 
ond processor are 140 + 2N tions 42 and 43, channel 2 uses 44 and 45, and so on to channel 7 which 
and 141 f 2N. uses 5^ an( j 57 -j^g processor starts an interrupt on channel TV by executing 

the instruction in location 40 + 2N. 

An instruction executed by the interrupt hardware in response to an 
interrupt request is referred to elsewhere in this manual as being executed 
"as an interrupt instruction". Some instructions, when so executed, perform 



2.13 PRIORITY INTERRUPT 2-75 

different functions than they do when executed in other circumstances. And 
the difference is not due merely to being executed in an interrupt location or 
in response (by the program) to an interrupt. To be an interrupt instruction, 
an instruction must be executed by the interrupt hardware, in location 
40 + 27V or 41 + 27V, because of a request on channel TV. 2.12 describes 
the two ways a BLKO is performed. If a BLKO is contained in an interrupt 
routine called by a JSR, it is not executed "as an interrupt instruction" even 
if the routine is stored within the interrupt locations. There are two 
categories of interrupt instructions. 

* Non-10 Instructions. After executing a non-IO interrupt instruction, the 
processor holds an interrupt on the channel and returns control to PC. Hence 
the instruction is usually a jump to a service routine. If the processor is in 
user mode and the interrupt instruction is a JSR, JSP, PUSHJ, JSA or JRST, 
the processor leaves user mode (the Monitor thus handles all interrupt rou- 
tines [2.15]). 

If the interrupt instruction is not a jump, the processor continues the 
interrupted program while holding an interrupt in other words it now 
treats the interrupted program as an interrupt routine. Eg the instruction 
might just move a word to a particular location. Such procedures are 
usually reserved for maintainence routines or very sophisticated programs. 
4 Block or Data IO Instructions. One or the other of two actions can result 
from executing one of these as an interrupt instruction. 

If the instruction in 40 + 27V is a BLKI or BLKO and the block is not 
finished (ie the count does not cause the left half of the pointer to reach 
zero), the processor holds and immediately dismisses an interrupt on the 
channel, and returns to the interrupted program. The same action results 
if the instruction is a DATAI or DATAO. 

If the instruction in 40 + 27V is a BLKI or BLKO and the count does reach 
zero, the processor continues to start the interrupt by executing the 
instruction in location 41 + 27V. This cannot be an IO instruction and the 
actions that result from its execution as an interrupt instruction are those 
given above for non-IO instructions. 

- 

CAUTION 

The execution, as an interrupt instruction, of a 
CONO, CONI, CONSO or CONSZ in location 
40 + 27V or any IO instruction in location 41 + 27V 
hangs up the processor. 

Dismissing an Interrupt. Automatic dismissal of an interrupt occurs only 
in a DATAI or DATAO, or in a BLKI or BLKO with an incomplete block. 
Following any non-IO interrupt instruction, the processor holds an interrupt 
until the program dismisses it, even if the interrupt routine is itself inter- 
rupted by a higher priority channel. Thus interrupts can be held on a num- 
ber of channels simultaneously, but from the time an interrupt is started 
until it is dismissed, no interrupt can be started on that channel or any 
channel of lower priority (requests, however, can be accepted on lower 
priority channels). 



2-76 



CENTRAL PROCESSOR 



2.13 



A routine dismisses the interrupt by using a JEN (JRST 12,) to return to 
the interrupted program (the interrupt system must be active when the JEN 
is given). This instruction restores the channel on which the interrupt is 
being held, so it can again accept requests, and interrupts can be started on 
it and lower priority channels. JEN also restores the flags, whose states were 
saved in the left half of the PC word if the routine was called by a JSR, 
JSP, or PUSHJ [2.9]. If flag restoration is not desired, a JRST 10, can 
be used instead. 

CAUTION 

An interrupt routine must dismiss the interrupt 
when it returns to the interrupted program, or its 
channel and all channels of lower priority will be 
disabled, and the processor will treat the new 
program as a continuation of the interrupt routine. 

Priority Interrupt Conditions. The program can control the priority in- 
terrupt system by means of condition IO instructions. The device code is 
004, mnemonic PI. 



CONO PI, 



Conditions Out, Priority Interrupt 



70060 


/ 


X 


Y 



12 13 14 



17 18 



35 



Perform the functions specified by E as shown (a 1 in a bit produces the 
indicated function, a has no effect). 



INITIATE 

INTERRUPT 

ON 



DEACTIVATE 

PI 



ACTIVATE 
PI 



CLEAR 
POWER 
FAILURE 
FLAG 


CLEAR 
PARITY 
ERROR 
FLAG 


OISA8LE[ENABLE 

PARITY ERROR 
INTERRUPT 

I 




CLEAR 
PI 
SYSTEM 


1 
SELEC 


TURN 
ON 

TED CHAN 


TURN 
OFF 

NELS 


\ 


/ 


1 


SELECT 
2 


CHANNE 
3 


LS FOR 
4 


BITS 24,25,26 

5 | 6 


7 


18 19 20 ' 21 22 23 


24 


25 


26 


27 28 29 


30 


31 


32 


33 34 


35 



Bits 18-21 are actually for 
processor conditions [2.14]. 



Notes. 
20 

21 

23 

24 



Prevent the setting of the Parity Error flag from requesting an 
interrupt on the channel assigned to the processor. 

Enable the setting of the Parity Error flag to request an interrupt 
on the channel assigned to the processor. 

Deactivate the priority interrupt system, turn off all channels, 
eliminate all interrupt requests that have already been accepted but 
are still waiting, and dismiss all interrupts that are currently being 
held. 

Request interrupts on channels selected by Is in bits 29-35, and 
force the processor to accept them even on channels that are off. 



2.13 



PRIORITY INTERRUPT 



2-77 



A request is lost if it is made by this means to a channel on which 
an interrupt is already being held. 

25 Turn on the channels selected by Is in bits 29-35 so interrupt 
requests can be accepted on them. 

26 Turn off the channels selected by Is in bits 29-35, so interrupt 
requests cannot be accepted on them unless made by a CONO PI, 
with a 1 in bit 24. 

27 Deactivate the priority interrupt system. The processor can then still 
accept requests, but it can neither start nor dismiss an interrupt. 

28 Activate the priority interrupt system so the processor can accept 
requests and can start, hold and dismiss interrupts. 



CONI PI, 



Conditions In, Priority Interrupt 



70064 


/ 


X 


Y 



12 13 14 



17 18 



35 



Read the status of the priority interrupt (and several bits of processor condi- 
tions) into the right half of location E as shown. 



PARITY ERROR 

INTERRUPT 

ENABLED 



POWER 


PARITY 


/ 


INTERRUPT IN PROGRESS ON CHANNELS 


PI 


CHANNELS ON 


FAILURE 


ERROR 












ACTIVE 


















1 


2 


3 


4 


5 | 6 


7 




1 


2 


3 


4 


5 


6 


7 


18 19 20 


21 


22 


23 


24 


25 26 


27 28 29 


30 


31 


32 


33 


34 


35 



Notes. 

18 Ac power has failed. The program should save PC, the flags and fast 
memory in core, and halt the processor. 

The setting of this flag requests an interrupt on the channel 
assigned to the processor. If the flag remains set for 5 ms, the 
processor is cleared. 

19 A word with even parity has been read from core memory. If bit 20 
is set, the setting of the Parity Error flag requests an interrupt on the 
channel assigned to the processor. 

28 The priority interrupt system is active. 

Channels that are on are indicated by Is in bits 29-35; Is in bits 21-27 
indicate channels on which interrupts are currently being held. 



Note that bits 18-20 actually 
read processor status condi- 
tions [2.14]. 



Timing. The time a device must wait for an interrupt to start depends on 
the number of channels in use, and how long the service routines are for 
devices on higher priority channels. If only one device is using interrupts, 



2-78 CENTRAL PROCESSOR 2.14 

it need never wait longer than the time required for the processor to finish 
the instruction that is being performed when the request is made. The 
maximum time can be considered to be about 1 5 /is for FDVL, but a ridicu- 
lously long shift could take over 35 /is. 

Special Considerations. On a return to an interrupted program, the proc- 
essor always starts the interrupted instruction over from the beginning. This 
causes special problems in a BLT and in byte manipulation. 

An interrupt can start following any transfer in a BLT. When one does, 
the BLT puts the pointer (which has counted off the number of transfers 
already made) back in AC. Then when the instruction is restarted following 
the interrupt, it actually starts with the next transfer. This means that if 
interrupts are in use, the programmer cannot use the accumulator that holds 
the pointer as an index register in the same BLT, he cannot have the BLT 
load AC except by the final transfer, and he cannot expect AC to be the 
same after the instruction as it was before. 

An interrupt can also start in the second effective address calculation in a 
two-part byte instruction. When this happens, Byte Interrupt is set. This 
flag is saved as bit 4 of a PC word, and if it is restored by the interrupt 
routine when the interrupt is dismissed, it prevents a restarted ILDB or 
IDPB from incrementing the pointer a second time. This means that the 
interrupt routine must check the flag before using the same pointer, as it 
now points to the next byte. Giving an ILDB or IDPB would skip a byte. 
And if the routine restores the flag, the interrupted ILDB or IDPB would 
process the same byte the routine did. 

Programming Suggestions. The Monitor handles all interrupts for user 
programs. Even if the User In-out flag is set, a user program generally cannot 
reference the interrupt locations to set them up. Procedures for informing 
the Monitor of the interrupt requirements of a user program are discussed in 
the Monitor manual. 

For those who do program priority interrupt routines, there are several 
rules to remember. 

4 No requests can be accepted, not even on higher priority channels, while 
a break is starting. Therefore do not use lengthy effective address calcula- 
tions in interrupt instructions. 

4 The interrupt instruction that calls the routine must save PC if there is to 
be a return to the interrupted program. Generally a JSR is used as it saves 
both PC and the flags, and it uses no accumulator. 

* The principal function of an interrupt routine is to respond to the situa- 
tion that caused the interrupt. Eg computations that can be performed 
outside the routine should not be included within it. 

* The routine must dismiss the interrupt (with a JEN) when returning to the 
interrupted program. The flags should be restored. 



2.14 PROCESSOR CONDITIONS 

There are a number of internal conditions that can signal the program by 
requesting an interrupt on a channel assigned to the processor. Flags for 



2.14 



PROCESSOR CONDITIONS 



2-79 



power failure and parity error are handled by the condition IO instructions 
that address the priority interrupt system [2.13]. The remaining flags are 
handled by condition instructions that address the processor. Its device code 
is 000, mnemonic APR or CPA. 



CONG APR, 



Conditions Out, Arithmetic Processor 



70020 


/ 


X 


Y 



12 13 14 



17 18 



35 



Perform the functions specified by E as shown (a 1 in a bit produces the 
indicated function, a has no effect). 



CLEAR CLEAR CLEAR 


CLEAR 


CLEAR 


PUSHDOWN MEMORY NONEXISTENT FLOATING 


OVERFLOW 


OVERFLOW PROTECTION MEMORY FLAG OVERFLOW 






FLAGj / 














CLEAR 




CLEAR 




/ 


DISABLE 


ENABLE 


CLEAR 


DISABLE! ENABLE 






DISABLE 


ENABLE 






PRIORITY 




ALL 
IN-OUT 
DEVICES 




ADDRESS 
BREAK 
FLAG 


\ 


/ 


CLOCK 
INTERRUPT 


CLOCK 
FLAG 


FLOATING 
OVERFLOW 
INTERRUPT 

i 






OVERFLOW 
INTERRUPT 






INTERRUPT 
ASSIGNMENT 
1 i 


16 19 20 


21 22 23 


24 


25 26 


27 28 29 


30 


31 32 


33 34 35 



Notes. 

Enabling a particular flag to interrupt means that henceforth the setting 
of the flag will request an interrupt on the channel assigned (by bits 33-35) 
to the processor. Disabling prevents the flag from triggering a request. 

A 1 in bit 19 produces the IO reset signal, which clears the control logic in 
all of the peripheral equipment (but affects neither the priority interrupt sys- 
tem, nor the processor flags cleared by this instruction or CONO PI,). 



CONI APR, 



Conditions In, Arithmetic Processor 



70024 |/ 


X 


Y 



12 13 14 



17 18 



35 



Read the status of the processor into the right half of location E as shown 
(all interrupt requests are made on the channel assigned to the processor). 



PUSHDOWN MEMORY NONEXISTENT CLOCK FLOATING FLOATING OVERFLOW OVERFLOW 
OVERFLOW PROTECTION MEMORY INTERRUPT OVERFLOW OVERFLOW INTERRUPT / 
FLAG ENABLED INTERRUPT ENABLED / 
\ \ / / ^U / / / 




\ 


USER 
IN-OUT 


ADDRESS 
BREAK 


\ 


/ 




/ 


CLOCK 
FLAG 




\ 


1 


TRAP 
OFFSET 


\ 


1 


PRIORITY 
INTERRUPT 
ASSIGNMENT 
1 1 


18 19 20 


21 22 23 


24 25 26 


27 28 29 


30 31 32 


33 34 35 



MAY 1968 



2-80 CENTRAL PROCESSOR 2.14 

Notes. 

19 Pushdown Overflow - in a PUSH or PUSHJ the count in AC left 
reached zero; or in a POP or POPJ the count reached - 1 . The setting 
of this flag requests an interrupt. 

20 User In-out even if the processor is in user mode, the restrictions 
on user instructions do not apply [2.15]. 

21 Address Break while the console address break switch was on, the 
processor requested access to the memoiy location specified by the 
address switches and the memory reference was for the purpose 
selected by the address condition switches as follows: 

The instruction switch was on and access was for retrieval of an 
instruction (including an instruction executed by an XCT or con- 
tained in an interrupt location or a trap for an unimplemented 
operation) or an address word in an effective address calculation. 

The data fetch switch was on and access was for retrieval of an 
operand (other than in an XCT). 

The write switch was on and access was for writing a word in 
memory. 

The setting of this flag requests an interrupt, at which time PC points 
to the instruction that was being executed or to the one following it. 

22 Memory Protection a user program attempted to access a memory 
location outside of its assigned area and the user instruction was ter- 
minated at that time. The setting of this flag requests an interrupt, 
at which time PC points either to the instruction that caused the 
violation or the one following it. 

23 Nonexistent Memory the processor attempted to access a memory 
that did not respond within 1 00 jus. The setting of this flag requests 
an interrupt, at which time PC points either to the instruction con- 
taining the unanswered reference or to the one following it. 

26 Clock this flag is set at the ac power line frequency and can thus 
be used for low resolution timing (the clock has high long term 
accuracy). If bit 25 is set, the setting of the Clock flag requests an 
interrupt. 

29 Floating Overflow this is one of the flags saved in a PC word, and 
the conditions that set it are given at the beginning of 2.9. If bit 28 
is set, the setting of Floating Overflow requests an interrupt, at which 
time PC points to the instruction following that in which the over- 
flow occurred. 

30 Trap Offset the processor is using locations 140-161 for unimple- 
mented operation traps and interrupt locations. 

32 Overflow this is one of the flags saved in a PC word, and the condi- 
tions that set it are given at the beginning of 2.9. If bit 31 is set, 
the setting of Overflow requests an interrupt, at which time PC 
points to the instruction following that in which the overflow 
occurred. 



Basic In-out Equipment 



The PDF- 10 contains three in-out devices as standard equipment: tape 
reader, tape punch, and teletype. These devices are used principally for 
communication between computer and operator using a paper medium, tape 
or form paper. 

The punch supplies output in the form of 8-channel perforated paper tape 
in either of two modes. In alphanumeric mode, 8-bit characters are proc- 
essed; in binary mode, 6-bit characters. The information punched in the 
tape can be brought into memory by the tape reader, which handles charac- 
ters in the same two modes. 

The program can type out characters on the teletype and can read charac- 
ters that have been typed in at the keyboard. This device has the slowest 
transfer rate of any, but it provides a convenient means of man-machine 
interaction. 



3.1 PAPER TAPE READER 

The reader processes 8-channel perforated paper tape photoelectrically at a 
speed of 300 lines per second. The device can operate in alphanumeric or 
binary mode, as specified by the or 1 state respectively of the Binary flag. 
In alphanumeric a single tape-moving command reads all eight channels from 
the first line encountered. In binary the device reads six channels from the 
first six lines in which hole 8 is punched and assembles the information into 
a 36-bit word. The interface contains a 36-bit buffer from which all data is 
retrieved by the processor. The reader device code is 1 04, mnemonic PTR. 



CONO PTR, 



Conditions Out, Paper Tape Reader 



7 1060 


/ 


X 


Y 



121314 1718 



35 



Set up the reader control register according to bits 30-35 of the effective 
conditions E as shown (a 1 in a flag bit sets the flag, a clears it). 









BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 

I I 



27 



28 



29 



30 



31 



32 



33 



34 



35 



3-1 



3-2 



BASIC IN-OUT EQUIPMENT 

CONI PTR, Conditions In, Paper Tape Reader 



3.1 



71064 


/ 


X 


Y 



121314 1718 35 

Read the status of the reader into bits 27 and 30-35 of location E as shown. 



TAPE 






BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 
i i 



27 



28 



29 



30 



31 



32 



33 



34 



35 



Placing the tape in motion sets the Tape flag and it remains set as long as the 
tape is in the read head. A in bit 27 indicates that the last time an attempt 
was made to read, the reader was out of tape. 



DATAI PTR, Data In, Paper Tape Reader 



7 1044 


/ 


X 


Y 



12 13 14 



17 18 



35 



Transfer the contents of the reader buffer into location E. Clear Done and 
set Busy. 



TAPE CHANNELS 



FEED 
HOLE 



TAPE MOTION 



Setting Busy clears the reader buffer, sets the Tape flag (if it is not already 
set) and places the reader in operation. If Binary is clear, all eight channels 
from the first line on tape are read into bits 28-35 of the buffer with 
channel 1 corresponding to bit 35 (the presence of a hole produces a 1 in the 
buffer). If Binary is set, the device reads only channels 1-6, but it reads the 
first six lines encountered in which channel 8 is punched (lines without a 
hole in channel 8 are skipped) and assembles them into a full word in the 
buffer. The first line is at the left in the word and channel 1 corresponds to 
the rightmost bit in each 6-bit byte. 

After the specified number of lines has been read, the reader clears Busy 
and sets Done, requesting an interrupt on the assigned channel. A DATAI 
brings the data into memory and also causes the reader to continue in opera- 
tion. The programmer must give a CONO to clear Busy if he does not want 
the reader to move the tape after the final DATAI is given. 

If the tape runs out or malfunctions while a read operation is in progress, 
the Tape flag is cleared and the reader shuts down. 

Timing. At 300 lines per second the reader takes 3.33 ms per alpha- 
numeric character, 20 ms per binary word if the binary characters are con- 
tiguous. After Done is set, the program has 1.6 ms to give a DATAI and 
keep the tape in continuous motion. Waiting longer causes the reader to 
shut down for 40 ms. Thus start-stop operation is limited to 25 lines per 
second. 



3.1 



PAPER TAPE READER 



3-3 



EXAMPLES. This program reads ten binary words (60 lines) from paper 
tape and stores them in memory beginning at location 4000. The block 
pointer is kept in accumulator PNT. 



NEXT: 



MOVE PNTJIOWD 12,4000] ;Put pointer in PNT 



CONO 

CONSO 

JRST 

BLKI 

JRST 

JRST 



PTR,60 

PTR,10 

.-1 

PTR,PNT 

.+2 

NEXT 



;Set up reader 
;Watch Done 

;Word ready, get it 

;Got all data 

;Go gack for next word 



If instead of just waiting we wish to continue our program while the data 
is coming in, we can use the priority interrupt. The following uses channel 4 
and signals the main program that the data is ready by setting bit 35 of 
accumulator F. 



MOVE 

MOVEM 

MOVE 

MOVEM 

CONO 

CONO 



TRZN 
JRST 



17, [BLKI PTRJIOWD 12,4000]] 

17,50 ;Set up 50 and 5 1 for channel 4 

17,[JSR DONE] 

17,51 

PTR,64 ;Set up reader on channel 4 

PI, 12210 ;Clear PI, then activate it and turn on 

; channel 4 

;Continue program 



.-1 



;Check if data ready when needed 
;Wait if necessary 



DONE: 

CONO PTR,0 

TRO F, 1 

JEN DONE 



Interrupt routine, block done 

;Stop tape 

;Set F bit 35 

; Dismiss and restore flags 



Operation. Tapes must be unoiled and opaque. The reader is located just 
above the console operator panel. To load it, place the fanfold tape stack 
vertically in the bin at the right, oriented so that the front end of the tape is 
nearer the read head and the feed holes are away from you. Lift the gate, 
take three or four folds of tape from the bin, and slip the tape into the rea- 
der from the front. Carefully line up the feed holes with the sprocket teeth 
to avoid damaging the tape, and close the gate. Make sure that the part of 
the tape in the left bin is placed to correspond to the folds, otherwise it will 
not stack properly. If the program requires that the Tape flag be set and it is 
not, briefly press the white feed button located on the face of the reader. 
After the program has finished reading the tape, run out the remaining 
trailer by pressing the feed button. 

Indicators for the reader are on the panel at the top of bay 1 (the panel is 



3-4 



BASIC IN-OUT EQUIPMENT 



3.1 



pictured in Appendix C). The paper tape reader lights in the second row 
from the bottom display the contents of the buffer. The PI assignment and 
flags are displayed in the PTR lights in the middle of the third row (EOT is 
the Tape flag). The remaining PTR lights are for maintenance. 



This loader is written for min- 
imum size and is quite com- 
plex. Do not approach it as a 
simple programming example. 



( "5 

H 
\f 



Readin Mode 

The only requirement (beyond those given in 2.12) for readin mode with 
paper tape is that the data must be in binary (hole 8 punched). To select 
the reader in the readin device switches, turn on the third from the left and 
the last on the right ( 1 04). 

The program below is the RIM 1 OB Loader, which is brought into the 
accumulators in readin mode, and then continues to read any number of 
blocks of binary data from the same tape. The tape is formatted as a series 
of blocks separated by a half-dozen lines of blank tape (tape with only feed 
holes punched). The first block is the loader in readin format. The rest of 
the tape contains any number of data blocks and ends with a transfer block. 
Each data block contains any number of words of program data, preceded 
by a standard IO block pointer for the data only, and followed by a check- 
sum, which is the sum of all the data words and the pointer. It is recom- 
mended that the number of data words per block be limited to twenty for 
ease in repositioning the tape in case of error. The transfer block is a JRST 
to the starting location of the program, followed by a throw-away word to 
stop the reader. 



ST: 

ST1: 

RD: 



A: 



TBL1: 



TBL2: 



ADR: 



XWD 

CONO 

HRRI 

CONSO 

JRST 

DATAI 

XCT 

XCT 

SOJA 

CAME 

ADD 
SKIPL 

JRST 
AOBJN 



; 14 10 words starting at location 1 
;Set up reader binary 
;PutRD+l in Y part of A 
;Watch Done 



JRST ST1 



7 CKSM=ADR+1 



-16,0 

PTR, 60 

A,RD+1 

PTR, 10 

.-1 

PTR,@TBL1-RD+1(A) ;First and last words in 

;ADR, data in block 
TBLl-RD-t-l(A) ;TBLl+2 first word, +1 data, 

;+0 checksum 
TBL2-RD+1(A) ;TBL2+2 JRST, +1 data, +0 

;bad checksum 
A, _ ;RD+1 first word, RD data, RD-1 

;last word 
CKSM,ADR ;Compare computed checksum with 

;one read 

CKSM, l(ADR) ;Add word read to checksum 

CKSM,ADR ;Put first word in CKSM, skip if 

;pointer 

;Halt if checksum bad 

;If data done, go to A; otherwise wait 

;for next word 

;Read in executes this. First and last 

;word of each block also put here 



4,ST 
ADR,RD 



3.2 



PAPER TAPE PUNCH 



The processor halts if a computed checksum does not agree with the tape. 
To reread a block, move the tape back to the preceding blank area and press 
the continue key. A halt following the transfer block is not an error many 
programs begin by halting. 



3.2 PAPER TAPE PUNCH 

The punch perforates 8-channel tape at speeds up to 50 lines per second. It 
can operate in alphanumeric or binary mode, as specified by the or 1 state 
respectively of the Binary flag; but in either mode a single tape-moving 
command punches only one line. Alphanumeric mode punches an 8-bit 
character supplied by the program; binary mode always punches channel 8, 
never punches channel 7, and punches a 6-bit character in the remaining 
channels. The interface contains an 8-bit buffer that receives data from the 
processor. The punch device code is 100, mnemonic FTP. 



3-5 



COIMO PTP, 



Conditions Out, Paper Tape Punch 



71020 


/ 


X 


Y 



12 13 14 



17 18 



35 



Set up the punch control register according to bits 30-35 of the effective 
conditions E as shown (a 1 in a flag bit sets the flag, a clears it). 









BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT 



27 



28 



29 



30 



31 



32 



33 



34 



35 



CO Ml PTP, 



Conditions In, Paper Tape Punch 



71024 


/ 


X 


Y 



121314 1718 

Read the status of the punch into bits 29-35 of location E as shown. 



35 







NO 
TAPE 


BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT 



27 28 29 30 31 32 33 

A 1 in bit 29 indicates that the punch is out of tape. 



34 



35 



3-6 



BASIC IN-OUT EQUIPMENT 

DATAO FTP, Data Out, Paper Tape Punch 



3.2 



71014 


/ 


X 


Y 



12 13 14 



1718 



35 



Load the contents of bits 28-35 of location E into the punch buffer. Clear 
Done and set Busy. 



A CONO need be given only to change Binary or the PI assignment; 
DATAO sets Busy while loading the buffer. Setting Busy places the punch in 
operation. If Binary is clear, one line is punched in tape from bits 28-35 of 
the buffer with bit 35 corresponding to channel 1 (a 1 in the buffer produces 
a hole in the tape). If Binary is set, channel 8 is punched, channel 7 is not 
punched, and the remaining channels are punched from bits 30-35 of the 
buffer with bit 35 corresponding to channel 1. After punching is complete, 
the device clears Busy and sets Done, requesting an interrupt on the assigned 
channel. 

Timing. If Busy is set when the punch motor is off, punching is auto- 
matically delayed 1 second while the motor gets up to speed. While the 
motor is on, punching is synchronized to a punch cycle of 20 ms. After 
Done sets, the program has 10 ms within which to give a new DATAO to 
keep punching at the maximum rate; after 10 ms punching is delayed until 
the next cycle. If Busy remains clear for 5 seconds the motor turns off. 

EXAMPLE. Suppose we wish to punch out the same information we read 
from tape in the examples of the previous section. We cannot use a BLKO 
as an interrupt instruction unless we first spread the 6-bit characters over 
sixty memory locations. The example uses channel 5 and assumes that other 
channels are already in use. 

MOVE A,[JSR PUNCH] 
MOVEM A, 5 2 ;Set up channel 5 

CONO PTP,55 ; Request interrupt for first word 

CONO PI, 2004 ;Turn on channel 5 

;Continue program 



PUNCH: 

BYPPNT: 
CNT: 



ILDB 
AOSL 
CONO 
DATAO 
JEN 

XWD 
tD-60 


A, BYPPNT 
CNT 
PTP,40 
PTP.A 
@PUNCH 

440600,4000 


; Interrupt routine 
;Put byte in A 
;Got all bytes? 
;Yes, prevent interrupt 
;Punch byte 

;Generate pointer here 
;Initialize count 


after last word 



Operation. The punch is located behind the reader; both are in a drawer 
that pulls out from the front of the console. Fanfold tape is fed from a box 
at the rear of the drawer. After it is punched, the tape moves into a storage 



3.3 TELETYPE 3-7 

bin from which the operator may remove it through a slot on the front. 
Pushing the feed button beside the slot clears the punch buffer and punches 
blank tape as long as it is held in. Busy being set prevents the button from 
clearing the buffer, so pressing it cannot interfere with program punching. 

To load tape, first empty the chad box behind the punch. Then tear off 
the top of a box of fanfold tape (the top has a single flap; the bottom of the 
box has a small flap in the center as well as the flap that extends the full 
length of the box). Set the box in the frame at the back and thread the tape 
through the punch mechanism. The arrows on the tape should be under- 
neath and should point in the direction of tape motion. If they are on top, 
turn the box around. If they point in the opposite direction, the box was 
opened at the wrong end; remove the box, seal up the bottom, open the top, 
and thread the tape correctly. 

To facilitate loading, tear or cut the end of the tape diagonally. Thread 
the tape under the out-of-tape plate, open the front guide plate (over the 
sprocket wheel), push the tape beyond the sprocket wheel, and close the 
front guide plate. Press the feed button long enough to punch about a foot 
and a half of leader. Make sure the tape is feeding and folding properly in 
the storage bin. Pushing the button labeled POWER sets No Tape, pushing 
it again clears the flag. It can be used to hold the program at bay while a 
tape is being loaded. 

To remove a length of perforated tape from the bin, first press the feed 
button long enough to provide an adequate trailer at the end of the tape 
(and also leader at the beginning of the next length of tape). Remove the 
tape from the bin and tear it off at a fold within the area in which only feed 
holes are punched. Make sure that the tape left in the bin is stacked to 
correspond to the folds; otherwise, it will not stack properly as it is being 
punched. After removal, turn the tape stack over so the beginning of the 
tape is on top, and label it with name, date, and other appropriate 
information. 

Indicators for the punch are the PTP lights in the top row of the panel 
at the top of bay 1 . The numbered lights display the last line punched. 



3.3 TELETYPE 

Two teletypewriter models are regularly available with the POP- 10 for use 
at the console: the KSR 35, which is capable of speeds up to ten characters 
per second, and the KSR 37, which can handle up to fifteen characters per 
second. The program can type out characters and can read in the characters 
produced when keys are struck at the keyboard. 

The teletype separates its input and output functions and in effect acts 
like two devices with a single device code: each has its own Busy and Done 
flags, but the two share a common interrupt channel. Placing the code for a 
character in the output buffer causes the teletype to print the character or 
perform the designated control function. Striking a key places the code for 
the associated character in the input buffer where it can be retrieved by the 
program, but it does nothing at the teletype unless the program sends the 
code back as output. 



3-8 



BASIC IN-OUT EQUIPMENT 



}3.3 



Character codes received from the teletype have eight bits wherein the 
most significant is an even parity bit. The Model 35 ignores the parity bit 
in characters transmitted to it. The Model 37 ignores the parity bit in a 
code for a printable character, but it performs no function when it receives 
a control code with incorrect parity. 

The Model 37 has the entire character set listed in the table in Appendix 
B. Lower case characters are not available on the Model 35, but transmitting 
a lower case code to the teletype causes it to print the corresponding upper 
case character. To go to the beginning of a new line the program must send 
both a carriage return, which moves the type box to the left margin, and 
a line feed, which spaces the paper. The teletype device code is 120, 
mnemonic TTY. 



CONO TTY, 



Conditions Out, Teletype 



7 1 220 


/ 


X 


Y 



12 13 14 



17 18 



35 



Set up the teletype control register according to bits 24-35 of the effective 
conditions E as shown (a 1 in bit 24 sets Test, a clears it; all other flag 
functions are produced by Is, Os have no effect). 



TEST 


CLEAR 
INPUT 


CLEAR 
INPUT 


CLEAR 
OUTPUT 


CLEAR 

OUTPUT 


SET 
INPUT 


SET 
INPUT 


SET 
OUTPUT 


SET 
OUTPUT 


PRIORITY INTERRUPT 
ASSIGNMENT 




BUSY 


DONE 


BUSY 


DONE 


BUSY 


DONE 


BUSY 


DONE 


1 I 



24 



25 



26 



27 



28 



29 



30 



31 



32 



33 



34 



35 



Setting Test connects the output buffer directly to the input buffer, allowing 
the program to check out the interface logic without the line and the device. 



24 



25 



CONI TTY, 



Conditions In, Teletype 



71 224 


7 


X 


Y 



121314 1718 



35 



Read the status of the teletype into bits 24 and 29-35 of location E as 
shown. 



TEST 










INPUT 
BUSY 


INPUT 
DONE 


OUTPUT 
BUSY 


OUTPUT 
DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 
i i 



26 



27 



28 



29 



30 



31 



32 



33 



34 



35 



DATAO TTY, Data Out, Teletype 



71214 



X 



12 13 14 



17 18 



35 



Load the contents of bits 28-35 of location E into the output buffer. Clear 
Output Done, set Output Busy, and enable the transmitter. 



3.3 TELETYPE 3-9 

DATAI TTY, Data In, Teletype 



71204 


/ 


X 


Y 



121314 1718 35 

Transfer the contents of the input buffer into bits 28-35 of location E. 
Clear Input Done. 



Output. A CONO need be given only to change the PI assignment; 
DATAO sets Output Busy and enables the transmitter while loading the 
buffer. Enabling the transmitter causes it to send the contents of the output 
buffer serially to the teletype. Completion of transmission clears Output 
Busy and sets Output Done, requesting an interrupt on the assigned channel. 

Input. Teletype reception requires no initiating action by the program 
except to supply a PI assignment. Striking a key transmits the code for the 
character serially to the input buffer. The beginning of reception sets Input 
Busy; completion clears Input Busy and sets Input Done, requesting an 
interrupt on the assigned channel. A DATAI brings the character into 
memory and clears Input Done. 

Timing. The Model 35 can type up to ten characters per second. After 
Output Done is set, the program has 9.09 ms to give a DATAO to keep 
typing at the maximum rate. After Input Done is set, the character is 
available for retrieval by a DATAI for 22.73 ms before another key strike 
can destroy it. 

The 37 can handle fifteen characters per second, 66.7 ms per character. 
After Output Done is set, the program has 6.67 ms to send a new character 
to maintain the maximum typing rate. After Input Done is set, the character 
is available for at least 1 ms. 

The sequence carriage return-line feed, when given in that order, allows 
sufficient time for the type box to get to the beginning of a new line. After 
tabbing, the program must wait for completion of the mechanical function 
by sending one or two rubouts. If the time is critical, the programmer 
should measure the time required for his tabs. Tabs are normally set every 
eight spaces (columns 9, 17, . . .) and require one rubout. 

Operation. The illustrations on the following two pages show the two 
teletype models. The teletype is actually two independent devices, keyboard 
and printer, which can be operated simultaneously. Power must be turned 
on by the operator. On the 35 the switch is beside the keyboard, and has an 
unmarked third position (opposite ON) which turns on power but with the 
machine off line so it can be used like a typewriter. A similar switch is 
located beneath the stand on the 37. 

The keyboard resembles that of a standard typewriter. Codes for printable 
characters on the upper parts of the key tops on the 35 are transmitted by 
using the shift key; most control codes require use of the control key. Those 
familiar with the 35 who are using the 37 for the first time should take a 
close look at the keyboard. On the 37 the shift is used for real upper case 
characters. The control key is used for some control characters, but many 






BASIC IN-OUT EQUIPMENT 




Teletype KSR 35 



have separate keys. Note also that both the keyboard arrangement and the 
labels differ somewhat. On both, the line feed (labeled "new line" on the 37) 
spaces the paper vertically at six lines to the inch, and must be combined 
with a return to start a new line. The local advance (feed) and return keys 
affect the printer directly and do not transmit codes. Appendix B lists the 
complete teletype code, ASCII characters, key combinations, and differences 
between the two models. 

Indicators for the teletype are the TTY lights in the second row of the 



TELETYPE 




panel at the top of bay 1. The numbered lights display the last character 
typed in from the keyboard (bit 8 is parity). The ACT lights indicate 
activity in the transmitter and receiver. The remaining lights display the PI 
assignment and flags (the Input and Output Done flags are labeled TTI 
FLAG and TTO FLAG). 

Teletype manuals supplied with the equipment give complete, illustrated 
descriptions of the procedures for loading paper, changing the ribbon, and 
setting horizontal and vertical tabs. The first two procedures are fairly 



Teletype KSR 37 



3-12 BASIC IN-OUT EQUIPMENT 3.3 

obvious: observe the paper or ribbon path and duplicate it. The other tasks 
are usually left for maintenance personnel. In any event, the best and easiest 
way to learn to do any of these things is to have someone who knows show 
you how. 



Appendices 



APPENDIX A 



INSTRUCTION AND DEVICE MNEMONICS 



The illustration on the next page shows the derivation of the instruction 
mnemonics. The two tables following it list all instruction mnemonics and 
their octal codes both numerically and alphabetically. When two mnemonics 
are given for the same octal code, the first is the preferred form, but the 
assembler does recognize the second. For completeness, UUOs are listed for 
user mode (an asterisk indicates a UUO mnemonic recognized by MACRO for 
communication with the PDF- 10 Time Sharing Monitor). All UUOs 
000-077 are identical when the processor is not in user mode. 

In-out device codes are included only in the alphabetic listing and are 
indicated by a dagger (f). Following the tables is a chart that lists the 
devices with their mnemonic and octal codes and DEC option numbers for 
both POP- 10 and PDP-6. A device mnemonic ending in the numeral 2 is 
the recommended form for the second of a given device, but such codes are 
not recognized by MACRO - they must be defined by the user. 



Al 



A2 



MNEMONICS 



E 


ive 








ADD 

SUBtract 
MULtiply 
Integer MULtiply 
DIVide 
Integer DIVide . 

Floating AdD 
Floating SuBtract 
Floating MultiPly 
Floating DiVide 

Floating SCale 
Double Floating N 
Unnormalized Floa 




Immediate 
to Memory 
to Both 

Long 
to Memory 
to Both 


e Magnitude 
e Swapped 

, 1 Right 1 (Right 1 
Half word \ f to i i T* 1 
[Left J [Left J 

BLock Transfer 
EXCHange AC and memory 


no effect 
Ones 

Zeros 
Extend sign 


to AC 
Immediate to AC 
to Memory 
to Self 


and Round- 


:gate 
ting Add 


use present pointer! , I LoaD Byte into AC 
Increment pointer f \ DePosit Byte in memory 

Increment Byte Pointer 


PUSH down) 
POP up J 


and Jump 








Arithmetic SHift I 
Logical SHift 
ROTate 


{~ 
Combined 




Zeros 
Ones 

SET to< ^ 

Memo 

Comp 
Comp 

AND ) 

inclusive OR j 

Inclusive OR 
exclusive OR 
EQuiValence 








AC 

AC Immediate 
Memory 
Both 


to Sub Rout 
and Save PC 
and Save A 
and Restore 
if Find Firs 
on Flag and 
on OVerflo 
Jump on CaRrY < 
on CaRrY 
on CaRrY 
on Floating 
and ReSTo 
and ReSTo 
and ENable 

HALT (JRST 4,; 
eXeCuTe 


ine 

Ac 
tOne 
CLear it 
w (JFCL 10.) 
3 (JFCL 4,) 
1 (JFCL 2,) 
(JFCL 6,) 
OVerflow (JFCL 1,) 
re 
re Flags (JRST 2,) 
PI channel (JRST 12,) 




ry 

lement of Ac 
lement of Memory , 

with Complement of Ac 
with Complement of Memory 
Complements of Both 


-to 


IP 






SKIP if memory) 


' never 
Less 
Equa 
Less 
Aiwa 
Greal 
Grea 
.Note 

jsitive 
egative 


[ 
Dr Equal 
ys 
er 
er or Equal 
qual 


JUMP if AC J 

Add One to ) f memory and Skip) ., 
Subtract One from j j AC and Jump J 

( Immediate ) 
Compare Ac { , ., } and skip if AC- 1 
I with Memory) 

Add One to Both halves of AC and Jump if ! -, 


DATAl 
BLocK 1 I In 

.JlOut 

CONditionsJ f . t ~ 
j 01 f \ all masked bits Zero 
>-in and Skip if { , , .. .-. 
I some masked bit One 


with Direct mask 

T with Swapped mask 
lest AC - . . . . 
Right with E 

Left with E 


No modification 

set masked bits to Zeros 
~ and skip 
set masked bits to Ones 

Complement masked bits 


never 
if all masked bits Equal 
if Not all masked bits equal 
Always 



NUMERIC LISTING 



A3 



INSTRUCTION MNEMONICS 
NUMERIC LISTING 



000 
001 



037 
040 
041 
042 
043 
044 
045 
046 
047 
050 
051 
052 
053 
054 
055 
056 
057 
060 
061 
062 
062 
063 
064 
065 
066 
067 
070 
071 
072 
073 
074 
075 
076 
077 
100 



127 
130 
131 



ILLEGAL 



USER 
UUO'S 



*CALL 
*INIT 



RESERVED 
FOR 

SPECIAL 
MONITORS 



*CALLI 
*OPEN 



RESERVED 
FOR DEC 



*RENAME 

*IN 

*OUT 

*SETSTS 

*STATO 

*STATUS 

*GETSTS 

*STATZ 

*INBUF 

*OUTBUF 

*INPUT 

"OUTPUT 

*CLOSE 

*RELEAS 

*MTAPE 

*UGETF 

*USETI 

*USETO 

*LOOKUP 

*ENTER 



UNASSIGNED 
CODES 



UFA 

DFN 



132 


FSC 


206 


MOVSM 


133 


IBP 


207 


MOVSS 


134 


ILDB 


210 


MOVN 


135 


LDB 


211 


MOVNI 


136 


IDPB 


212 


MOVNM 


137 


DPB 


213 


MOVNS 


140 


FAD 


214 


MOVM 


141 


FADL 


215 


MOVMI 


142 


FADM 


216 


MOVMM 


143 


FADE 


217 


MOVMS 


144 


FADR 


220 


IMUL 


145 


FAORI A 


221 


IMULI 


146 


FAD^M 


222 


IMULM 


147 


FADRB 


223 


IMULB 


150 


FSB 


224 


MUL 


151 


FSBL 


225 


MULI 


152 


FSBM 


226 


MULM 


153 


FSBB 


227 


MULB 


154 


FSBR 


230 


IDIV 


155 


FSBRI A 


231 


IDIVI 


156 


FSBRM 


232 


IDIVM 


4-57 


FSBRB 


233 


IDIVB 


160 


FMP 


234 


DIV 


161 


FMPL 


235 


DIVI 


162 


FMPM 


236 


DIVM 


163 


FMPB 


237 


DIVB 


164 


FMPR 


240 


ASH 


165 


FMPRI A 


241 


ROT 


166 


FMPRM 


242 


LSH 


167 


FMPRB 


243 


JFFO 


170 


FDV 


244 


ASHC 


171 


FDVL 


245 


ROTC 


172 


FDVM 


246 


LSHC 


173 


FDVB 


247 




174 


FDVR 


250 


EXCH 


175 


FDVRI A 


251 


BLT 


176 


FDVRM 


252 


AOBJP 


177 


FDVRB 


253 


AOBJN 


200 


MOVE 


254 


JRST 


201 


MOVEI 


25410 


JRSTF 


202 


MOVEM 


25420 


HALT 


203 


MOVES 


25450 


JEN 


204 


MOVS 


255 


JFCL 


205 


MOVSI 


25504 


JFOV 



MAY 1968 



A4 



MNEMONICS 



25510 


JCRY1 


25520 


JCRYO 


25530 


JCRY 


25540 


JOV 


256 


XCT 


257 




260 


PUSHJ 


261 


PUSH 


262 


POP 


263 


POPJ 


264 


JSR 


265 . 


JSP 


266 


JSA 


267 


JRA 


270 


ADD 


271 


ADDI 


272 


ADDM 


273 


ADDB 


274 


SUB 


275 


SUBI 


276 


SUBM 


277 


SUBB 


300 


CAI 


301 


CAIL 


302 


CAIE 


303 


CAILE 


304 


CAIA 


305 


CAIGE 


306 


CAIN 


307 


CAIG 


310 


CAM 


311 


CAML 


312 


CAME 


313 


CAMLE 


314 


CAMA 


315 


CAMGE 


316 


CAMN 


317 


CAMG 


320 


JUMP 


321 


JUMPL 


322 


JUMPE 


323 


JUMPLE 


324 


JUMPA 


325 


JUMPGE 


326 


JUMPN 


327 


JUMPG 


330 


SKIP 


331 


SKIPL 


332 


SKIPE 



333 


SKIPLE 


334 


SKIPA 


335 


SKIPGE 


336 


SKIPN 


337 


SKIPG 


340 


AOJ 


341 


AOJL 


342 


AOJE 


343 


AOJLE 


344 


AOJA 


345 


AOJGE 


346 


AOJN 


347 


AOJG 


350 


AOS 


351 


AOSL 


352 


AOSE 


353 


AOSLE 


354 


AOSA 


355 


AOSGE 


356 


AOSN 


357 


AOSG 


360 


SOJ 


361 


SOJL 


362 


SOJE 


363 


SOJLE 


364 


SOJA 


365 


SOJGE 


366 


SOJN 


367 


SOJG 


370 


SOS 


371 


SOSL 


372 


SOSE 


373 


SOSLE 


374 


SOSA 


375 


SOSGE 


376 


SOSN 


377 


SOSG 


400 


SETZ 


400 


CLEAR 


401 


SETZI 


401 


CLEARI 


402 


SETZM 


402 


CLEARM 


403 


SETZB 


403 


CLEARB 


404 


AND 


405 


ANDI 


406 


ANDM 


407 


ANDB 



410 
411 
412 
413 
414 
415 
416 
417 
420 
421 
422 
423 
424 
425 
426 
427 
430 
431 
432 
433 
434 
434 
435 
435 
436 
436 
437 
437 
440 
441 
442 
443 
444 
445 
446 
447 
450 
451 
452 
453 
454 
455 
456 
457 
460 
461 
462 
463 
464 



ANDCA 

ANDCAI 

ANDCAM 

ANDCAB 

SETM 

SETMI 

SETMM 

SETMB 

ANDCM 

ANDCMI 

ANDCMM 

ANDCMB 

SETA 

SETAI 

SETAM 

SETAB 

XOR 

XORI 

XORM 

XORB 

IOR 

OR 

IORI 

ORI 

IORM 

ORM 

IORB 

ORB 

ANDCB 

ANDCBI 

ANDCBM 

ANDCBB 

EQV 

EQVI 

EQVM 

EQVB 

SETCA 

SETCAI 

SETCAM 

SETCAB 

ORCA 

ORCAI 

ORCAM 

ORCAB 

SETCM 

SETCMI 

SETCMM 

SETCMB 

ORCM 



NUMERIC LISTING 



A5 



465 


ORCMI 


466 


ORCMM 


467 


ORCMB 


470 


ORCB 


471 


ORCBI 


472 


ORCBM 


473 


ORCBB 


474 


SETO 


475 


SETOI 


476 


SETOM 


477 


SETOB 


500 


HLL 


501 


HLLI 


502 


HLLM 


503 


HLLS 


504 


HRL 


505 


HRLI 


506 


HRLM 


507 


HRLS 


510 


HLLZ 


511 


HLLZI 


512 


HLLZM 


513 


HLLZS 


514 


HRLZ 


515 


HRLZI 


516 


HRLZM 


517 


HRLZS 


520 


HLLO 


521 


HLLOI 


522 


HLLOM 


523 


HLLOS 


524 


HRLO 


525 


HRLOI 


526 


HRLOM 


527 


HRLOS 


530 


HLLE 


531 


HLLEI 


532 


HLLEM 


533 


HLLES 


534 


HRLE 


535 


HRLEI 


536 


HRLEM 


537 


HRLES 


540 


HRR 


541 


HRRI 


542 


HRRM 


543 


HRRS 


544 


HLR 


545 


HLRI 



546 


HLRM 


547 


HLRS 


550 


HRRZ 


551 


HRRZI 


552 


HRRZM 


553 


HRRZS 


554 


HLRZ 


555 


HLRZI 


556 


HLRZM 


557 


HLRZS 


560 


HRRO 


561 


HRROI 


562 


HRROM 


563 


HRROS 


564 


HLRO 


565 


HLROI 


566 


HLROM 


567 


HLROS 


570 


HRRE 


571 


HRREI 


572 


HRREM 


573 


HRRES 


574 


HLRE 


575 


HLREI 


576 


HLREM 


577 


HLRES 


600 


TRN 


601 


TLN 


602 


TRNE 


603 


TLNE 


604 


TRNA 


605 


TLNA 


606 


TRNN 


607 


TLNN 


610 


TON 


611 


TSN 


612 


TONE 


613 


TSNE 


614 


TDNA 


615 


TSNA 


616 


TDNN 


617 


TSNN 


620 


TRZ 


621 


TLZ 


622 


TRZE 


623 


TLZE 


624 


TRZA 


625 


TLZA 


626 


TRZN 



627 


TLZN 


630 


TDZ 


631 


TSZ 


632 


TDZE 


633 


TSZE 


634 


TDZA 


635 


TSZA 


636 


TDZN 


637 


TSZN 


640 


TRC 


641 


TLC 


642 


TRCE 


643 


TLCE 


644 


TRCA 


645 


TLCA 


646 


TRCN 


647 


TLCN 


650 


TDC 


651 


TSC 


652 


TDCE 


653 


TSCE 


654 


TDCA 


655 


TSCA 


656 


TDCN 


657 


TSCN 


660 


TRO 


661 


TLO 


662 


TROE 


663 


TLOE 


664 


TROA 


665 


TLOA 


666 


TRON 


667 


TLON 


670 


TOO 


671 


TSO 


672 


TDOE 


673 


TSOE 


674 


TDOA 


675 


TSOA 


676 


TDON 


677 


TSON 


70000 


BLKI 


70004 


DATAI 


70004 


RSW 


70010 


BLKO 


70014 


DATAO 


70020 


CONO 


70024 


CONI 


70030 


CONSZ 


70034 


CONSO 



A6 



MNEMONICS 



INSTRUCTION MNEMONICS 
ALPHABETIC LISTING 



fADC 
ADD 
ADDB 
ADDI 
ADDM 
AND 
ANDB 
ANDCA 
ANDCAB 
ANDCAI 
ANDCAM 
ANDCB 
ANDCBB 
ANDCBI 
ANDCBM 
ANDCM 
ANDCMB 
ANDCMI 
ANDCMM 
ANDI 
ANDM 
AOBJN 
AOBJP 
AOJ 
AOJA 
AOJE 
AOJG 
AOJGE 
AOJL 
AOJLE 
AOJN 
AOS 
AOSA 
AOSE 
AOSG 
AOSGE 
AOSL 
AOSLE 
AOSN 

tAPR 
ASH 
ASHC 
BLKI 
BLKO 



024 
270 
273 
271 
272 
404 
407 
410 
413 
411 
412 
440 
443 
441 
442 
420 
423 
421 
422 
405 
406 
253 
252 
340 
344 
342 
347 
345 
341 
343 
346 
350 
354 
352 
357 
355 
351 
353 
356 

000 
240 
244 
70000 
70010 



BLT 

CAI 

CAIA 

CAIE 

CAIG 

CAIGE 

CAIL 

CAILE 

CAIN 
*CALL 
*CALLI 

CAM 

CAMA 

CAME 

CAMG 

CAMGE 

CAML 

CAMLE 

CAMN 

tcci 

fCDP 

fCDR 
CLEAR 
CLEARS 
CLEARI 
CLEARM 

*CLOSE 
CONI 
CONO 
CONSO 
CONSZ 

tCPA 

tCR 
DATAI 
DATAO 

tDC 

tDCSA 

tDCSB 

fDF 
DFN 

fDIS 
DIV 
DIVB 
DIVI 



251 

300 

304 

302 

307 

305 

301 

303 

306 

040 

047 

310 

314 

312 

317 

315 

311 

313 

316 
014 
110 
114 

400 

403 

401 

402 

070 

70024 

70020 

70034 

70030 
000 
150 

70004 

70014 
200 
300 
304 
270 

131 
130 

234 

237 

235 



DIVM 


236 


fDLS 


240 


DPB 


137 


fDSK 


170 


fDTC 


320 


fDTS 


324 


*ENTER 


077 


EQV 


444 


EQVB 


447 


EQVI 


445 


EQVM 


446 


EXCH 


250 


FAD 


140 


FADE 


143 


FADL 


141 


FADM 


142 


FADR 


144 


FADRB 


147 


FADRI 


145 


FADRM 


146 


FDV 


170 


FDVB 


173 


FDVL 


171 


FDVM 


172 


FDVR 


174 


FDVRB 


177 


FDVRI 


175 


FDVRM 


176 


FMP 


160 


FMPB 


163 


FMPL 


161 


FMPM 


162 


FMPR 


164 


FMPRB 


167 


FMPRI 


165 


FMPRM 


166 


FSB 


150 


FSBB 


153 


FSBL 


151 


FSBM 


152 


FSBR 


154 


FSBRB 


157 


FSBRI 


155 


FSBRM 


156 



ALPHABETIC LISTING 



A7 



FSC 


132 


*GETSTS 


062 


HALT 


25420 


HLL 


500 


HLLE 


530 


HLLEI 


531 


HLLEM 


532 


HLLES 


533 


HLLI 


501 


HLLM 


502 


HLLO 


520 


HLLOI 


521 


HLLOM 


522 


HLLOS 


523 


HLLS 


503 


HLLZ 


510 


HLLZI 


511 


HLLZM 


512 


HLLZS 


513 


HLR 


544 


HLRE 


574 


HLREI 


575 


HLREM 


576 


HLRES 


577 


HLRI 


545 


HLRM 


546 


HLRO 


564 


HLROI 


565 


HLROM 


566 


HLROS 


567 


HLRS 


547 


HLRZ 


554 


HLRZI 


555 


HLRZM 


556 


HLRZS 


557 


HRL 


504 


HRLE 


534 


HRLEI 


535 


HRLEM 


536 


HRLES 


537 


HRLI 


505 


HRLM 


506 


HRLO 


524 


HRLOI 


525 


HRLOM 


526 


HRLOS 


527 


HRLS 


507 


HRLZ 


514 


HRLZI 


515 



HRLZM 


516 


HRLZS 


517 


HRR 


540 


HRRE 


570 


HRREI 


571 


HRREM 


572 


HRRES 


573 


HRRI 


541 


HRRM 


542 


HRRO 


560 


HRROI 


561 


HRROM 


562 


HRROS 


563 


HRRS 


543 


HRRZ 


550 


HRRZI 


551 


HRRZM 


552 


HRRZS 


553 


IBP 


133 


IDIV 


230 


IDIVB 


233 


IDIVI 


231 


IDIVM 


232 


IDPB 


136 


ILDB 


134 


IMUL 


220 


IMULB 


223 


IMULI 


221 


IMULM 


222 


*IN 


056 


*INBUF 


064 


*INIT 


041 


"INPUT 


066 


IOR 


434 


IORB 


437 


IORI 


435 


IORM 


436 


JCRY 


25530 


JCRYO 


25520 


JCRY1 


25510 


JEN 


25460 


JFCL 


255 


JFFO 


243 


JFOV 


25504 


JOV 


25540 


JRA 


267 


JRST 


254 


JRSTF 


25410 


JSA 


266 



JSP 

JSR 

JUMP 

JUMPA 

JUMPE 

JUMPG 

JUMPGE 

JUMPL 

JUMPLE 

JUMPN 

* LOOKUP 

tLPT 
LSH 
LSHC 

fMDF 
MOVE 
MOVEI 
MOVEM 
MOVES 
MOVM 
MOVMI 
MOVMM 
MOVMS 
MOVN 
MOVNI 
MOVNM 
MOVNS 
MOVS 
MOVSI 
MOVSM 
MOVSS 

*MTAPE 

tMTC 

fMTM 

fMTS 
MUL 
MULB 
MULI 
MULM 

*OPEN 
OR 
ORB 
ORCA 
ORCAB 
ORCAI 
ORCAM 
ORCB 
ORCBB 
ORCBI 



265 

264 

320 

324 

322 

327 

325 

321 

323 

326 

076 
124 

242 

246 
260 

200 

201 

202 

203 

214 

215 

216 

217 

210 

211 

212 

213 

204 

205 

206 

207 

072 
220 
230 
224 

224 

227 

225 

226 

050 

434 

437 

454 

457 

455 

456 

470 

473 

471 



A8 



MNEMONICS 



ORCBM 

ORCM 

ORCMB 

ORCMI 

ORCMM 

ORI 

ORM 

*OUT 

*OUTBUF 

"OUTPUT 

tPI 

fPLT 
POP 
POPJ 

fPTP 

fPTR 
PUSH 
PUSHJ 

*RELEAS 

*RENAME 
ROT 
ROTC 
RSW 
SETA 
SETAB 
SETAI 
SETAM 
SETCA 
SETCAB 
SETCAI 
SETCAM 
SETCM 
SETCMB 
SETCMI 
SETCMM 
SETM 
SETMB 
SETMI 
SETMM 
SETO 
SETOB 
SETOI 
SETOM 

*SETSTS 
SETZ 
SETZB 
SETZI 
SETZM 
SKIP 



472 

464 

467 

465 

466 

435 

436 

057 

065 

067 
004 
140 

262 

263 
100 
104 

261 

260 

071 

055 

241 

245 

70004 

424 

427 

425 

426 

450 

453 

451 

452 

460 

463 

461 

462 

414 

417 

415 

416 

474 

477 

475 

476 

060 

400 

403 

401 

402 

330 



SKIPA 


334 


SKIPE 


332 


SKIPG 


337 


SKIPGE 


335 


SKIPL 


331 


SKIPLE 


333 


SKIPN 


336 


SOJ 


360 


SOJA 


364 


SOJE 


362 


SOJG 


367 


SOJGE 


365 


SOIL 


361 


SOJLE 


363 


SOJN 


366 


SOS 


370 


SOSA 


374 


SOSE 


372 


SOSG 


377 


SOSGE 


375 


SOSL 


371 


SOSLE 


373 


SOSN 


376 


*STATO 


061 


*STATUS 


062 


*STATZ 


063 


SUB 


274 


SUBB 


277 


SUBI 


275 


SUBM 


276 


TDC 


650 


TDCA 


654 


TDCE 


652 


TDCN 


656 


TON 


610 


TDNA 


614 


TONE 


612 


TDNN 


616 


TDO 


670 


TDOA 


674 


TDOE 


672 


TDON 


676 


TDZ 


630 


TDZA 


634 


TDZE 


632 


TDZN 


636 


TLC 


641 


TLCA 


645 


TLCE 


643 



TLCN 


647 


TLN 


601 


TLNA 


605 


TLNE 


603 


TLNN 


607 


TLO 


661 


TLOA 


665 


TLOE 


663 


TLON 


667 


TLZ 


621 


TLZA 


625 


TLZE 


623 


TLZN 


627 


tTMC 


340 


tTMS 


344 


TRC 


640 


TRCA 


644 


TRCE 


642 


TRCN 


646 


TRN 


600 


TRNA 


604 


TRNE 


602 


TRNN 


606 


TRO 


660 


TROA 


664 


TROE 


662 


TRON 


666 


TRZ 


620 


TRZA 


624 


TRZE 


622 


TRZN 


626 


TSC 


651 


TSCA 


655 


TSCE 


653 


TSCN 


657 


TSN 


611 


TSNA 


615 


TSNE 


613 


TSNN 


617 


TSO 


671 


TSOA 


675 


TSOE 


673 


TSON 


677 


TSZ 


631 


TSZA 


635 


TSZE 


633 


TSZN 


637 


UFA 


130 


*UGETF 


073 



ALPHABETIC LISTING A9 

*USETI 074 tUTS 214 XORB 433 

*USETO 075 XCT 256 XORI 431 

fUTC 210 XOR 430 XORM 432 



A10 



MNEMONICS 







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u 










O 


3 o It 


10 >- 

co 3 


s 


CJ 
O 










ro 


2 5 |i 


Q ^ 

O O 


^~ 

UJ 


& 














5? 


to O a: 


a. 















O t UJ 


S ^ I 


^ 


p 










. 


^ t-> J5&: 


' \ ^ 


CO o 


*- co 










CM 


<t gz 


Q- 


S ^ 















rf o 




Z 


UJ 












9 1 


*,2 ? 


CP 

<x 


a. 
g 













5 . <o 

2 - 


(O 


f 


UJ 
Q 










CM 


o o-E 
o S 


t- i 




O 












S 


^.2 ^ 


! 


o 












o 


S o: 

















1-1 -iJE 


' g g 


in 
CO 












^r 


iffi 




I 












*~ 


o o! 


<_> o 
















Q- Z 


















O 


3 


s 

X 












o 


S g 



=UJ 


& Q. | 



J__ 














cto 

00 



















O-. 

10 


o 5 


10 
















a 


ID 


o 












c^ 


^ tt ^ 


^ r\j o 


to QQ 










S 


* * (E 5: 

^ 


Q_ 2 ,jj 

Q. 


o 2 


CO 
O 
CO 












u>~ 


tO k- 


u? 














BE 


S 5 


HI 

C^ -i 












g 


8:2 i 


Q- 

^ Q.Q. 




CO 











</> 


s SS 


"^ 


o 


o 












ui" - 


>2 - 


(0 


10 











^ZiSio 

U-O Q 



(O 



i I 5 > 5 

o- a. -S S " 

o o .. S 

Q- Q. S o o 



3 s ^ i 

e E 



c I 
o c *- 



> ^ 

a. a 

a. a. 

i E 

I I 



X<->_ a, 
t-OO g 



s: 



CO 

o 



o 



UJ 
Q 



S30IA3Q QdVQNViS 030 



S30IA30 TVI33dS 



APPENDIX B 



INPUT-OUTPUT CODES 



The table beginning on the next page lists the complete teletype code. The 
lower case character set (codes 140-176) is not available on the Model 35, 
but giving one of these codes causes the teletype to print the corresponding 
upper case character. Other differences between the 35 and 37 are men- 
tioned in the table. The definitions of the control codes are those given by 
ASCII. Most control codes, however, have no effect on the console teletype, 
and the definitions bear no necessary relation to the use of the codes in con- 
junction with the POP- 10 software. 

The line printer has the same codes and characters as the teletype. The 
64-character printer has the figure and upper case sets, codes 040-137 
(again, giving a lower case code prints the upper case character). The "96"- 
character printer has these plus the lower case set, codes 040-176. The 
latter printer actually has only ninety-five characters unless a special charac- 
ter is "hidden" under the delete code, 177. A hidden character is printed by 
sending its code prefixed by the delete code. Hence a character hidden under 
DEL is printed by sending the printer two 1 77s in a row. 

Besides printing characters, the line printer responds to ten control charac- 
ters, HT, CR, LF, VT, FF, OLE and DC 1-4. The 1 28-character printer uses 
the entire set of 7-bit codes for printable characters, with characters hidden 
under the ten control characters that affect the printer and also under null 
and delete. In all cases, prefixing DEL causes the hidden character to be 
printed. The extra thirty-three characters that complete the set are ordered 
special for each installation. 

The first page of the table of card codes [pages B6-8] lists the column 
punch required to represent any character in the two DEC codes. The octal 
codes listed are those used by the PDF- 10 software. In other words, when 
reading cards, the Monitor translates the column punch into the octal code 
shown; when punching cards, it produces the listed column punch when 
given the corresponding code. The remaining pages of the table show the 
relationship between the DEC card codes and several IBM card punches. 
Each of the column punches is produced by a single key on any punch for 
which a character is listed, the character being that which is printed at the 
top of the card. 



Bl 



B2 INPUT-OUTPUT CODES 

TELETYPE CODE 

Even 7-Bit 
Parity Octal 
Bit Code Character Remarks 

000 NUL Null, tape feed. Repeats on Model 37. Control shift P on Model 35. 

1 001 SOH Start of heading; also SOM, start of message. Control A. 
1 002 STX Start of text; also EGA, end of address. Control B. 

003 ETX End of text; also EOM, end of message. Control C. 

1 004 EOT End of transmission (END); shuts off TWX machines. Control D. 

005 ENQ Enquiry (ENQRY); also WRU, "Who are you?" Triggers identification 

("Here is ... ") at remote station if so equipped. Control E. 

006 ACK Acknowledge; also RU, "Are you ... ?" Control F. 

1 007 BEL Rings the bell. Control G. 

1 010 BS Backspace; also FEO, format effector. Backspaces some machines. 

Repeats on Model 37. Control H on Model 35. 

Oil HT Horizontal tab. Control I on Model 35. 

012 LF Line feed or line space (NEW LINE); advances paper to next line. Repeats 

on Model 37. Duplicated by control J on Model 35. 

1 013 VT Vertical tab (VTAB). Control K on Model 35. 

014 FF Form feed to top of next page (PAGE). Control L. 

1 015 CR Carriage return to beginning of line. Control M on Model 35. 
1 016 SO Shift out; changes ribbon color to red. Control N. 

017 SI Shift in; changes ribbon color to black. Control O. 

1 020 OLE Data link escape. Control P (DCO). 

02 1 DC 1 Device control 1 , turns transmitter (reader) on. Control Q (X ON). 

022 DC2 Device control 2, turns punch or auxiliary on. Control R (TAPE, 

AUX ON). 

1 023 DC3 Device control 3, turns transmitter (reader) off. Control S (X OFF). 

024 DC4 Device control 4, turns punch or auxiliary off. Control T (TAPE, 

AUX OFF). 

1 025 NAK Negative acknowledge; also ERR, error. Control U. 
1 026 SYN Synchronous idle (SYNC). Control V. 

027 ETB End of transmission block; also LEM, logical end of medium. Control W. 

030 CAN Cancel (CANCL). Control X. 

1 031 EM End of medium. Control Y. 
1 032 SUB Substitute. Control Z. 

033 ESC Escape, prefix. This code is generated by control shift K on Model 35, 

but the Monitor translates it to 175. 

1 034 FS File separator. Control shift L on Model 35. 

035 GS Group separator. Control shift M on Model 35. 



TELETYPE CODE 



B3 



Even 
Parity 
Bit 


7-Bit 
Octal 
Code 


Character Remarks 





036 


RS Record separator. Control shift N on Model 35. 


1 


037 


US Unit separator. Control shift O on Model 35. 


1 



1 




040 
041 
042 
043 
044 


SP Space. 


* 
$ 


1 


045 


% 


1 


046 


& 





047 


Accent acute or apostrophe. 





050 


( 


1 


051 


) 


1 


052 


* Repeats on Model 37. 





053 


+ 


1 


054 


, 





055 


Repeats on Model 37. 





056 


Repeats on Model 37. 


1 


057 


/ 




1 


060 
061 



1 


1 


062 


2 





063 


3 


1 


064 


4 





065 


5 





066 


6 


1 


067 


7 


1 


070 


8 





071 


9 





~072 




1 


073 


j 





074 


< 


1 


075 


= Repeats on Model 37. 


1 


076 


> 





077 


? 


1 



100 
101 


"IS?" 

A 





102 


B 



B4 



INPUT-OUTPUT CODES 



Even 
Parity 
Bit 

1 

1 
1 



1 
1 



1 




1 



1 
1 



1 




1 
1 




1 



1 
1 




7-Bit 
Octal 
Code 

103 
104 
105 
106 
107 
110 
111 
112 
113 
114 
115 
116 
117 
120 
121 
122 
123 
124 
125 
126 
127 
130 
131 
132 
133 
134 
135 
136 
137 


Character Remarks 

C 
D 
E 
F 
G 
H 
I 
J 
K 
L 
M 
N 

P 
Q 

R 

S 
T 
U 
V 

w 

X Repeats on Model 37. 
Y 

z 

[ Shift K on Model 35. 
\ Shift L on Model 35. 
] Shift M on Model 35. 
t 
- Repeats on Model 37. 




1 
1 



1 




1 


140 
141 
142 
143 
144 
145 
146 
147 


Accent grave, 
a 
b 
c 
d 
e 
f 
g 



TELETYPE CODE 



B5 



Even 


7-Bit 




Parity 


Octal 




Bit 


Code 


Character 


1 


150 


h 





151 


i 





152 


j 


1 


153 


k 





154 


1 


1 


155 


m 


1 


156 


n 





157 


o 


1 


160 


P 





161 


q 





162 


r 


1 


163 


s 





164 


t 


1 


165 


u 


1 


166 


V 





167 


w 





170 


X 


1 


171 


y 


1 


172 


z 





173 


{ 


1 


174 


1 





175 


I Jt 





176 


Q^ 


1 


177 


DEL 



Remarks 



Repeats on Model 37. 



This code generated by ALT MODE on Model 35. 

This code generated by ESC key (if present) on Model 35, but the 
Monitor translates it to 175. 

Delete, rub out. Repeats on Model 37. 



REPT 

PAPER ADVANCE 
LOCAL RETURN 
LOCLF 
LOCCR 

INTERRUPT, BREAK 
PROCEED, BRK RLS 
HERE IS 



Keys That Generate No Codes 

Model 35 only: causes any other key that is struck to repeat continuously 
until REPT is released. 

Model 37 local line feed. 

Model 37 local carriage return. 

Model 35 local line feed. 

Model 35 local carriage return. 

Opens the line (machine sends a continuous string of null characters). 

Break release (not applicable). 

Transmits predetermined 21 -character message. 



MAY 1968 



B6 



INPUT-OUTPUT CODES 

CARD CODES 



PDF- 10 


Character 


ASCII 


DEC 029 


DEC 026 


Space 


040 


None 


None 


\ 


041 


1182 


1287 


n 


042 


87 


085 


# 


043 


8 3 


086 


$ 


044 


1183 


1183 


% 


045 


084 


087 


& 


046 


12 


1187 


t 


047 


8 5 


8 6 


( 


050 


12 8 5 


084 A 


) 


051 


1185 


12 8 4 A 


* 


052 


1184 


1184 


+ 


053 


12 8 6 


12 


> 


054 


083 


083 


- 


055 


11 


11 




056 


12 8 3 


12 8 3 


/ 


057 


1 


1 





060 








1 


061 


1 


1 


2 


062 


2 


2 


3 


063 


3 


3 


4 


064 


4 


4 


5 


065 


5 


5 


6 


066 


6 


6 


7 


067 


7 


7 


8 


070 


8 


8 


9 


071 


9 


9 


" 


072 


8 2 


1 1 8 2 or 1 1 


J 


073 


1186 


082 


< 


074 


12 8 4 


12 8 6 


= 


075 


8 6 


8 3 


> 


076 


086 


1186 


1 


077 ; 


087 


12 8 2 or 12 


Binary 


7 9 






Mode Switch 


12 


2468 




End of File 


12 1 


1 1 





Character 



A 

B 

C 

D 

E 

F 

G 

H 

I 

J 

K 

L 

M 

N 

O 

P 

Q 
R 

S 
T 

U 

V 

w 

X 

Y 

z 

[ 
\ 

] 
t 



POP- 10 
ASCII 

100 
101 
102 
103 
104 
105 
106 
107 
110 
111 
112 
113 
114 
115 
116 
117 
120 
121 
122 
123 
124 
125 
126 
127 
130 
131 
132 
133 
134 
135 
136 
137 



DEC 029 DEC 026 



84 
12 1 
12 2 
12 3 
12 4 
12 5 
12 6 
12 7 
12 8 
12 9 
11 
11 
11 
1 
1 



1 

2 
3 
4 
5 
6 
7 



2 
3 



1 
1 
1 

1 9 


4 
5 
6 
7 
8 
9 
12 8 2 
1187 
082 
12 8 7 
085 



8 4 
12 1 
12 2 
12 3 
124 
12 5 
12 6 
12 7 
12 8 
12 9 



1 

1 
1 
1 

2 
3 
4 
5 
6 
7 
8 
9 

11 8 
8 7 

12 8 
8 5 
8 2 



The octal codes given above are those generated by the Monitor from the column punches. The card 
reader interface actually supplies a direct binary equivalent of the column punch, as listed in the following 
two pages. 



MAY 1968 



CARD CODES 



B7 



Column 








Punch 


Character 


Octal 




None 


Space 


0000 










1000 




1 


1 


0400 




2 


2 


0200 




3 


3 


0100 




4 


4 


0040 




5 


5 


0020 




6 


6 


0010 




7 


7 


0004 




8 


8 


0002 




9 


9 


0001 




12 1 


A 


4400 




12 2 


B 


4200 




123 


C 


4100 




124 


D 


4040 




12 5 


E 


4020 




12 6 


F 


4010 




12 7 


G 


4004 




128 


H 


4002 




Column 


026 Data 


026 




Punch 


Processing 


Fortran 


029 


12 


& 


+ 


& 


11 


- 


- 


- 


12 








11 








8 2 






| 


8 3 


# 


= 


# 


8 4 


@ 


- 


@ 


8 5 






t 


8 6 






= 


8 7 






it 


12 8 2 






t 


12 8 3 


. 


. 


. 


12 8 4 


D 


) 


< 


12 8 5 






( 


12 8 6 






+ 



Column 






Punch 


Character 


Octal 


12 9 


I 


4001 


11 1 


J 


2400 


11 2 


K 


2200 


11 3 


L 


2100 


11 4 


M 


2040 


11 5 


N 


2020 


11 6 





2010 


11 7 


P 


2004 


11 8 


Q 


2002 


11 9 


R 


2001 


1 


/ 


1400 


2 


S 


1200 


3 


T 


1100 


04 


U 


1040 


5 


V 


1020 


6 


w 


1010 


7 


X 


1004 


8 


Y 


1002 


9 


Z 


1001 



DEC 026 



@ 

t 

I 

\ 

9 



DEC 029 

& 



# 
@ 



Octal 

4000 
2000 
5000 
3000 
0202 
0102 
0042 
0022 
0012 
0006 
4202 
4102 
4042 
4022 
4012 



B8 



INPUT-OUTPUT CODES 



Column 
Punch 

12 8 7 

1182 

1183 

1184 

1185 

1186 

1187 

082 

083 

084 

085 

086 

087 

12 11 1 

12 2 4 6 8 

7 9 



026 Data 
Processing 



$ 
* 



026 
Fortran 



S 
* 



029 



H 
See note 



DEC 026 

! 

$ 

* 

& 



DEC 029 

t 

$ 

) 

> 
\ 



End of File End of File 

Mode Switch Mode Switch 

Binary Binary 



Octal 

4006 
2202 
2102 
2042 
2022 
2012 
2006 
1202 
1102 
1042 
1022 
1012 
1006 
7400 
5252 



NOTE: There is a single key for the 082 punch on the 029 but printing is suppressed. 

The Monitor translates the octal code for the 1 2 punch in DEC 026 to 4202 (which corresponds to a 
1282 punch), and the code for 1 1 to 2202 (11 82). 



APPENDIX C 
MISCELLANY 

Instruction Flow Simplified C2 

Word Formats C3 

Instruction Timing Flow Chart C4 

In-out Device Bit Assignments C6 

Indicator Panels Cg 

Powers of Two CIO 



Cl 



C2 



MISCELLANY 



INSTRUCTION 
FETCH 



INTERRUPT 
REQUEST 



BYT INSTR. 



CALCULATION 



BLKI, BLKO 



DATA 
FETCH 



POINTER DONE IN 



INTERRUPT 
REQUEST 



INSTRUCTION 
EXECUTION 



BYTE, BLKI, BLK 



DATA 
STORE 




INSTRUCTION FLOW SIMPLIFIED 



WORD FORMATS 



C3 



BASIC INSTRUCTIONS 



INSTRUCTION CODE 
(INCLUDING MODE) 


A,F 


/ 


X 


Y 





8 9 


12 13 14 17 18 35 

IN-OUT INSTRUCTIONS 


1 1 

1 1 




DEVICE CODE 


INSTRUCTION 
CODE 


/ 


X 


Y 





2 


3 






9 


10 


12 13 14 


17 18 35 

PC WORD 


FLAGS 


000 

1 1 




I 


PC 













12 13 


17 18 35 

1 


OVERFLO* 


CARRY 




CARRY 

1 


FLOATING 
OVERFLOW 


BYTE 
INTERRUPT 


USER 


USER 

IN-OUT 


FLOATING N0 
IINHFP- u 

U ?g,W DIVIDE 







1 


2 


3 




4 


5 6 7 8 9 10 11 12 

BIT POINTER [XWDj 


SOURCE 


ADDRESS 


DESTINATION ADDRESS 



35 



BLKI/BLKO POINTER, PUSHDOWN POINTER, DATA CHANNEL CONTROL WORD [lOWDJ 



-WORD COUNT 



ADDRESS -I 



BYTE POINTER 



POSITION P 


SIZE 5 




/ 


X 


Y 



11 12 13 14 



17 16 



35 



BYTE STORAGE 









BYTE 


NEXT BYTE 
i 



y>-P 



35 



FIXED POINT OPERANDS 



SIGN 

1- 



BINARY NUMBER (TWOS COMPLEMENT) 



1 



35 



FLOATING POINT OPERANDS 



SIGN 
0* 
1- 



EXCESS 128 EXPONENT 
(ONES COMPLEMENT! 



FRACTION (TWOS COMPLEMENT) 



1 



35 



LOW ORDER WORD IN DOUBLE LENGTH FLOATING POINT OPERANDS 



EXCESS 128 EXPONENT-27 
IN POSITIVE FORM 



LOW ORDER HALF OF FRACTION (TWOS COMPLEMENT) 



1 



8 9 



WORD FORMATS 



C4 



MISCELLANY 



. "(.10 L 

| "IF IN USER MODE [ 




INSTRUCTION TIMING 
FLOW CHART 



INSTRUCTION TIMING 



C5 



INSTRUCTION EXECUTION 



t > 




' 






i 


-^ <^ACCUMULATOR^> 
JYES 

<^ REGISTERS ^> 
TNO 


Boolean (except ANDCA, ANOC8, ORCA. ORCB). 
Hall Words (except HLR. HLRI, HRL. HRLI), MOVE. 
MOVS, EXCH. JFCL. JRST, JSP, XCT, UUO .27 
ANDCA. ANDCB. ORCA. ORCB. HLR. HLRI. 
HRL. HRLI. JSR. JSA. JRA. Test class .62 
MOVN, MOVM. ADD. SUB. AOBJP. AOBJN. 
CAM. CAI. SKIP. JUMP. AOJ, AOS, SOJ, SOS 45 
PUSH.PUSHJ. POP, POPJ, OFN .80 
JFFO .80 +. 19 times number ol leading Os mod 18 
BLT .69 + .11 if User) + memory write access + .52 
If not done + .09 and go to C3 
IBP .38 + .26 if overflow word boundary 
LDB, DPB First time .61 + .15 per size count OotoCl 

ILOB.IDPB First time .74 { * \\ P," s "' count } GoloCl 
\ + .26 if overflow I 

ILOB. LDB Second time .45 + .15 per position count 
IDPB, DPB Second time .95 + .15 per position count 

Shittgroup t 23 R 6 hi f + 15pershift 

MUL 6.02 +.13 per transition 
Average except MULI 8.36 118 transitions or 2.34) 
IMUL 6.34 > 13 per transition 
Average except IMULI 7.51 19 transitions for 1.17) 
FMP 6.39 +.13 per transition 
Average except FMPRI 8.21 (14 transitions for 1.82) 
Note: Immediate mode multiplication has only half the average number of transitions 
DIV.IDIV 13.78 
FSC 1.52 + .25 per shift to normalije 
FAD. UFA 2.38 ^ ]5 Pshilt tounnormali 
Average 4 33 ' Bel ' normal " e 
FSB Same as FAD* .18 
Rounding (except divide) only when actually done +.96 
Long mode (except divide) +.69 
FDVR.FOV (except FDVL) 12.00 
FDVL with fast ACs 13.28 
FDVL without fast ACs 12.32 + .11 if User) + memory read access* .89 

CONO, CONI. CONSO. CONSZ. DATAO, OATAI .12 Then wait until 4 50 has passed since last here 
CONO.CONI, DATAO. DATAI +2.69 
CONSO, CONSZ +2.90 
BLKO.BLKI .60 Then turn into DATAO. OATAI and go to C2 


i7+*(.m 

* IF IN USER M( 


IDE 


\ 


/-f -tor 


MEMORY WRI 
ACCESS (CHA 


re ( $ ( TJ\_ 

rr i) , 


E 




i > 


I 


| 


NO MEMORY READ / PAUSf 
RESULT ACCESS 


RESULT TO 
MEMORY 


M**^ 


| 


.17+ *(.11) 
" IF IN USER MODE 


1 * 


"\ J MEMORY WRITE 
p* 1 *^ ACCESS (CHART 1) 


T 




.xfX 

_NO/STORE SECON 

"^^ACCUMULATO 
JYES 

* ^ <L REGISTERS 

^^v 


l> 
> 


1 


CHART 1 




.17+ "(.III 
* IF IN USER MO 


DE 


| 




MEMORY MAie Mete MBIO KMIB * 


MEMORY WRI1 


E O^VW n^ 


PROCESSORS OR'"MULTI SINOLE MULTI (BUILT L fN) 




CYCLE 1 00 1.65 165 
READ ACCESS* .55 60 70 21 
WRITE ACCESS* .20 .20 .30 .21 






) 




M INCLUDING 20 FT OF CABLE DELAY 
t FAST REGISTERS 
ALL TIMES ARE 15% 


(DONE] 



C6 



MISCELLANY 









- 



n 



S? 



ri 









nm 



SiS5 



fe!>? 



tu ^( 

3s! 






! 



tat 



i S : 
5*| ; 



J,p? 



*Sp Jp 

dim? 



Sa 



IN-OUT DEVICE BIT ASSIGNMENTS 



C7 







C8 



MISCELLANY 



(N 



ed 

M 



o 



o 



03 
O 



o> 
o 

s 

OH 
O 






s 

4-> 

c 



C3 

c- 



03 
CJ 

3 



c 

OH 
O 







INDICATOR PANELS 



C9 



a. 
o 
o 



o 

6 



o 

o 



<u 

n) 

a. 



T3 

C 




05 

m 

VO 



O 

E 



-> 
v* 

O 

o 

03 



o 



O 



CIO MISCELLANY 

POWERS OF TWO 



1 1.0 

2 1 05 
4 2 0.25 
8 3 0.125 

16 4 0.062 5 

32 5 0.031 25 

64 6 0.015 625 

128 7 0.007 812 5 

256 8 0.003 906 25 

512. 9 0.001 953 125 

1 024 10 0.000 976 562 5 

2 048 11 0.000 488 281 25 
4 096 12 0.000 244 140 625 

8 192 13 0.000 122 070 312 5 

16-384 14 0.000 061 035 156 25 

32 768 15 0.000 030 517 578 125 



65 53& 16 0.000 015 258 789 062 b 

131 072 17 0.000 007 629 394 531 25 

262 144 18 0.000 003 814 697 265 625 

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8 388 608 23 0.000 000 119 209 289 550 781 25 

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4 294 967 296 32 0.000 000 000 232 830 643 653 869 628 906 25 
8 589 934 592 33 0.000 000 000 116 415 321 826 934 814 453 125 

17 179 869 184 34 0.000 000 000 058 207 660 913 467 407 226 562 5 

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68 719 476 736 36 0.000 000 000 014 551 915 228 366 851 806 640 625 

137 438 953 472 37 0.000 000 000 007 275 957 614 183 425 903 320 312 5 

274 877 906 944 38 0.000 000 000 003 637 978 807 091 712 951 660 156 25 

549 755 813 888 39 0.000 000 000 001 818 989 403 545 856 475 830 078 125 

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8 796 093 022 208 43 0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5 

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144 115 188 075 855 872 57 0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125 

288 230 376 151 711 744 58 0000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562 5 

576 460 752 303 423 488 59 0000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 25 

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4 611 686 018 427 387 904 62 0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 285 156 25 
9 223 372 036 854 775 808 63 0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125 

18 446 744 073 709 551 616 64 0000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085 571 289 062 5 

36 893 488 147 419 103 232 65 0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542 785 644 531 25 

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590 29 r y 810 358 705 651 712 69 0000 000 000 000 000 000 001 694 065 894 508 600 678 136 645 001 359 283 924 102 783 203 125 

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