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A REPORT ON THE . onlo Numerical Ir.tsgratoa
v., \. of Work undtr Contract Between
T-ho Uti Scji ool of, S2
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I IV
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part :: technical description c toy Dr. Hurry D. Hue
Mooro School of Elootrit. a .. -v tng
Un Ivors ity oC Po» r i .»
o, m
"•? ^follows:
I onsist s
c <r-
5 S
c
p;
ng lianual . en&nca Manual al Deecrlp I - Chapter^ .ical Description . a II - Chapt vical Description Included w. ianual and Part
are all dr :. Le 0.3 below) which
reports. -■ -,'al assumes accet
drawings.
to have a g*>
urt a t>l \>.9 Technical Dcscr:, u
solves witr, or oircuit
.-standing of how the e. -.s or tho circuitsi sea
y. Part II is Intended for t-
standing of th circuits. Its organization, to
■
^of Port I ..j as co make cross referencing botwee
?he T C '• -rating Manual contai \B 5fbr oporatiru, the ENIAC, It includos very Litl le ^hence aasustea familiarity with Part I of tn* }The ENIAC Li .t-n: >•.■"• Manual includes descripW . procodures /or testing, as well as a list o:
parts, as
! ' - ' : E ■' ?£. onderst - . the«i i it file e
■ '.. -,o8>. v»h.
concerning tftam- sge of oxicts" sic . ietailod under* ■> , duplicated thi 5 .a isy, i
f Inst ructions material, a*kd -on of tae EfilxC. rarious cest unit*, ard . . *a sources of
^trouble. It ii,->uraes a complete under standi ng •'• '» of the QUaC lt
^ a lowvlodge o both Tarts I and II of the J c£ a s >g of thc sti^c»
The Report in the KlUkC and tna conipi-;tt; file o . drawings
constitute a complete description and act of in< — & ><■• or operation and maintenance of vho .iachine. The drawings carrj a ttuc r of tho form PX-n-m. The following tables ,,,dve the classification ace rding .> this numbering systom.
|
T^BLE 0.1 |
|
|
Values of n |
Diviaic/i |
|
1 |
General |
|
2 |
Tost Equipment |
|
3 |
Racks and Panels |
|
fc |
Trays, Cables, Kdr.ptors, arid ", >aa -oxes |
|
5 |
Accumulators |
|
6 |
High Speed Multipli r |
|
7 |
Function Table |
|
8 |
Master Programmer |
|
9 |
Cycling Unit and Initio lag Un. |
|
10 |
Divider and Square |
|
11 |
Constant Transmitter |
|
12 |
Printer |
|
13 |
Power Supplies |
Values of m
101-200 201-300 301-400 101-500
TABLE 0.2
Suojt
Hiring Diagrams Mechanical Drawings Report Drawings Illustration Problem Stt-Ops.
The reader of this report Ui be primarily interested in the typo3 of drawings listed in the following paragraphs, * table on page 4 gives the corresponding drawing number for each unit of the EMIAC.
1) Front Panel Drawings. These drawings show in some detail the switches, sockets, etc., for each panel of each unit. They contain the essential instructions for setting up a problem on the ENIaC.
2) Front View Drawings. There is one of these drawings for **ac* kind of panel used in the various units of the ENIaC, These show the relative position of the trays and tne location of the various .^eon lights. Since these drawings show the neon lights, they can be used to check the proper operation of the various units.
3) Block Diagrams, These drawings illustrate the logical essentials of the internal circuits of each unit. That is, resistors, condensers, and some other electrical details are not shown; but complete channels (paths of pulses or gates representing numbers or program signals) are shown in all their •nultiplicity. These drawings will b f interest to the so <*c are interested
ir. Parts [ and rt of the Pech; ' •■■- Report*
4) Crosd-section Diagj ws. These drawings ar ,.ctr >nic3,lly comply except that onlv one channel is shown where there is more tnan one. Thus, these drawings show every resistor "nd condenser and any other electronic elements . belonging to any circuit. These drawings will be of particular interest to
the maintenance personnel and to those reading Part II of the technical report.
5) Detail Drawings. All other drawings of the ENIAC come under this heading. A complete file of drawings is available it I \ loeation »i t! EKIAC*
r-...-L- ».3 ei in m urns
|
Unit |
Front Panel |
Front v'iev. |
Block Diagram |
Cross - Section |
|
Initiating Unit |
PX-9-302 9-302R |
PX-9-305 |
PX-9-307 |
|
|
Cycling Unit |
PX-9-303 9-303R |
PX-9-304 |
PX-9-307 |
|
|
Accumulator |
PX-5-301 |
PX-5-305 |
FX-5-304 |
PX-5-115 |
|
Multiplier |
PX-6-302 6-302R 6-303 6-303R 6-304 6-304R |
PX-6-309 |
PX-6-303 |
PX-6-112* 6-112B " Tx-/~uY~~" 7-: 18 |
|
Function Table |
PX-7-302 7-302R 7-303 i.303_R |
ft 7-305 |
PX-/-304 |
|
|
Divider and Square Rooter |
PX-10-301 10-301R |
PX-lb-302 |
PX-lO-304 |
|
|
Constant Trans- mitter |
PX-U-302 11-302R 11-303 11-303R 11-304 11-304R |
PX-li-306 |
PX-ll-307 |
PX-11-116 11-309 (C.T. and R.) |
|
Printer |
PX-12-301 12-301R 12-302 12-303 P) 6-31 8-301R 3-302 8-302R |
PX-12-306 PX-8-30J |
PX-12-307 |
PX-12-115 |
|
Master Pro- gramner |
PX-2-3CM, |
i i ^8-10. |
||
|
Other drawings Floor Plan A.C. Wirin ISJ Reader plugboard I I |
of particular i PX-1-33 g PX-1-3C and PX-11-1 PX-11-3 nt-r connect! on nt -r ■■ mi ction |
nterest: 2 IS.! Punch and PX-12-112 3 Plu^bo:.rd PX- 12-305 19 Poise ..r-TOlificr vjid PX-4-302 0 5 Block Diagram PX-4-301 of Multiplier end accumulators PX-6-311 of f/ivi-icr -.:d Accumulators ''X- 10-307 |
The front riew drawings and the large front panel art sings (whose nwafeers do <ot end with }<R") are bound is a part of the Op ~r-. tor1 a lianual.
Included with the report is a folder containing all the drawings listed in the above table except the large front panel (see above). A plete file of drawings is available at the location of the EMIAC.
8L£ IF CONTESTS I. GENER*l ! SCRIftj ■:■, OF CHS SNIAC
1.1. BRIEF DESCRIPTION OF THE ENIAC Page 2
1.1.1. Units of the ENIAC 3
1.1.2,. Digit Trunks 7
1.1.3. Program Trunks 8
1.1.4. Static Cables 8
1.2. FUNDAMENTAL ELECTRONIf UNITS OF THE ENIAC 8
1.2.1. Flip-flop 9
1.2.2. Counters U
1.2.3. Gate Tubes 13
1.2.4. Buffer Tubes 15
1.2.5. Cathode Followers 16
1.2.6. Inverter Tubes 16
1.2.7. Pulse Standsrdizcr 17
1.2.8. Trans-sitter 19
1.2.9. Receiver Plug-ia Unit 20 1.2. 0 Transceiver Mw; -in ;;;>it 21
1.3. BLOCK AND CROSS SECTION DLhGRaIIS 22
II. INITIATING UNIT
2,1, STARTING *ND STOPPING SEQUENCE AND INITIAL CLEhR 2
2.1.1. Norrail Initial Conditions 2
2.1.2, Complete Starting Sequence I*
u
? »^»3t 2le.'trc ' ■ Sequence p^gg 6
2.1,4a The d-c on Sequence 7
2.1.5. The Initial Clear 8
2.2. INITIATING PULSE PROGRAM CONTROL li
2.3. OTHER FEATURES 12
2.3.1. Selective Clear Controls 12
2*3.2. Reader and Printer Pr^^ram Controls 13
2.4. TESTING FEATURES
III. CYCLING UNIT
3.0. INTRODUCTION 2
3.1. THE OSCILLATOR AND PULSE FORMERS
3.1.1. The Oscillator
3.1.3. The on-beat plug-in unit
3J ,4. The off-beat plua-ln unU
3.2. THE RING AND ITS ASSOCIATED GATES AND FLIP-FLOPS
3.2.1. The tens pulses (10P)
3.2.2. The 1. 2, 2» , U and 9 pulses
3.2.3. The one-prined pulse (l'P)
3.2.4. The carry clear gate (CCG)
3.2.5. The reset pulse (RP) 8
3.2.6. The central program pulse (CPD) 8
ui
*,3. CHE P"Ji>-£ MTO ORE Art?iTI0N TIUE OPERATIOH 8
3.3.1. One addition time operation 9
3.3.2. One pulse tine operation 9
IV. ACCUMULATOR
4.0. IHTRODUCTIOH 2
4.U" THE PROGRAM CONTROL CIRCUITS 5
4.1.1. General description of a ncp.~rrpe-i.t program
control circuit 5
4.1.2. General description of a repeat progran circuit 6
4.2. THE COMMON PROGRAMMING CIRCUITS 7
4.2.1. The receiving circuits 7
4.2.2. The add and subtract transmission circuits 8
4.2.3. General description of the clear circuits 9
4.2.4. ~ description of the interconnection features 10
4.3. NU^RICkL CIRCUITS
4.3.1. Gener 1 description of i :oc^.de plug-in unit ll
4.3.2. General description of a PM - Clear plug-in unit 15
V. THE HIGH SPEED MULTIPLIER
5.0. iirrRODUCTioii 2
5*1* PROGRaU CONTROL CIRCUITS 3
5 . | . 1 . [hej uffer j lug-in units 3
5.1.2. i-n-.-jcelygra 4
5.1.3. Prograa control switches 4
t*
5.2. COMMON PROGRAMMING CIRCUITS
5.2.1. The multiplier ring
5.3. INITIAL CLEARING
5.4. NUMERICAL CIRCUITS
5.^.1. The multiplier selector
5.4.2. The tables and the table gates
5.4.3. The lairltiplicand sele ctors
5.5. EXAMPLE
6.0. INTRODUCTION
VI, DIVIDER AND SqOARE-SOOTER
6.1. PROGRAM CONTROLS
6.1.1. Numerator and denominator receive switches
6.1.2. The numerator and denominator clear switches 6 , ! , "3 , T nterlock Switch
6.1.4. Anew -,r disposal switch
6.1.5 . Round-off Switch
6.1.6. Root-Divide and Place Switch
6.2. THE COMMON PROGRAMMING CIRCUITS
6.2.1. The pulse source circuits
6.2.2. The program ring circuits
6.2.3. The Sign Indication Circuit
6.2.4. The over-dr-.ft circuit
6.2.5. The add-subtract circuit
Pag« 6 6
10 10 10
11
13
iv
. VI, DIVIDER AND SQUARE-ROOTER
5.2. COMMON PROGRAMING CIRCUITS
5.2.1. The multiplier ring
5.3. INITIAL CLEARING
5.4. NUMERICAL CIRCUITS
5.4.1. The multiplier selector
5.4.2. The tables and the tabic gates
5.4.3. The nmltiplic-uid selectors
5.5l EXAMPLE
6.0. INTRODUCTION
6.1. PROGRAM CONTROLS
6.1.1. Numer'tor and denominator receive switches
6.1.2. The ngagrator ^nd denominator clear switches
6.1.3. Interlock Switch
6.1.4. 4hgwgr disposal switch
6.1.5. Round- off Switch
6.1.6. Root-Divide ur.d Place Switch
THE COMMON PROGR..MMING CIRCUITS
6.2.1. The pulse source circuits
6.2.2. The progr-Ji ring circuits
6.2.3. The Sim Indication Circuit
6.2.4. The ovut-dr -ft circuit
6.2.5. The .dd-subtrict circuit
6.2.
Page 6 6
10 10 10
11
13
3 3 4 5 5 6 6
7
8 10 12 14
15
6.2.6. The roundoff circuit p^ iy
6.2.7. The root correction circuit • ifl
6.2.8. The shift circuit 19
6.2.9. The interlock and clear circuits 20
6.2.10. The; initial cloar 21
6.3. NIOSICAL CIRCUITS 21
6.3.1. The- quotient-place ring 21
6.4, EXAMPLES 2k
6.4.1. A division exanplc 24
6.4.2. n square root exanplc 28
VH. FUNCTION T.^BLE
7.0* INTRODUCTION *
7.1. THE PROGLuJ CONTROL CIRCUITS 3
7.1.1. The Transceivers 3
7.1.2. The rgunent Reception Switch 3
7.1.3. The Prograra Switch 4
7.1.4. The Repeat Switch 6
f*2. THE COLUMN PROGRAMMING CIRCUITS 6
7.2.1. The Prolan Ring 6
7.2.2. The ..rgunent Flip-flop 8
7.2.3. The »rid and Subtr-ct Flip-flops ?.nd the Pulse Gates 8
7.2.4. Use of tht; function T^blo for Progr'.ming 9
7.2.5. Initial Clear 10
7.3. THE NUMERIC/J. CIRCUITS Page 10
7.3.1. The Argument Rings 10
7.3.2. The Table Input Gates 12
7.3.3. The Portable Table 13
7.3.4. Table Output Gates 13
7.3.5. The PH Haster Switches 14
7.3.6. The constant switches and the delete switches 14
7.3.7. The Subtract Pulse Switches 15
7.3.8. The output transoitters 15
7.3.9. adapters 16
VIII. THE CONSTANT TRANSMITTER *ND Htl RENTER
8.1. CONSTAT TRANSMITTER PROGR^ CONTROLS 2
8.1.1. The groups of numbers 2
8.1.2. Transceivers 3
8.1.3. The Progran Control Circuits 3
8.2. READER PtfOGRnH CONTROLS 6
8.2.1. Starting 6
8.2.2. Resetting 6
8.2.3. The Finish Signal 7
8.2.4. Interlock 7
8.3. HUSERIC^L CIRCUITS OF T!E CONSTANT TR«HSHITTER 8
8.3.1, The Storage Rcloys and their Gates 9
8 . 3 .2 , The Constant and Pll Set Switches U
▼ii
8.4. THE ISi READEH
8.4.1. The a-c Circuits
8.4.2. Starting Clrtujta
8.4.3. Numerical Circuits
8.4.4. group Selection
8.4.5. Reset Control and Reset Shunt
8.4.6. Coding Cam
8.4.7. Reset Signal
8.4.8. Finish Signal
U. PRINTER AND IBM GANG PUNCH
9.1* PROGRAM CONTROL CIRCUITS
9.1.1. The Printing Switches
9.1.2. Starting Circuit
9.1.3. Rosct and Program Output 9.1.4* Ths Interlock Cam 9.1.5. Initial Clear
9.2. THL NUMERICAL CIRCUITS OF THE PRINTER
Pag. 13 13 13 15 16 16 17 18 18
9.3. THE ISl GANG PUNCH
9.3.1. The a-c Circuit
9.3.2. The Starting Circuit
9.3.3. The Colunn Splits (PM Circuits)
9.3.4. The Punch Magnets \
9.3.5. The Baltfr
9.3.6. The Plug-beard
10 10 U 12 12 13 13
viii
X. IIaSTER PROQu^SR
10.1. INTRODUCTION Page
10.2.' DECADE COUNTER CIRCUITS
10.2.1. Decode ring
10.3. THE STEPPER ORCtaTS
10 . 3 .1. Ths stepper ring
10 . 3 . 2 . The_ program transmitters
10.3.3. The program receiving circuit
10.3.4. The coincidence gates
10.4. ASSOCIATION SKETCHING
XI. THE TRANSaSSION SYSTEM AKD SPECIaL DEVICES
11.1. TftAXS AND TRUNKS
11.1.1. Trays
11.1.2. Jumpers
11.1.3. Ti-urks and Lines
11.1.4. Loid Boxes
11.1.5. Lor.d Units
11.2. DELETERS
11.3. SHIFTERS
11.4. PULSE r2?PLIFIER UNIT
11.5. ST.^IC OUTPUTS
11.6. SPECLJ, DEVICES Page 8
11.6.1. Special Program Jumpers 9
11.6.2* Accunulator Interconnection Cables &
11.6.3. Multiplier Interconnection Cables 6
11.6.4. Divider Interconnection Cables and /idapters 9 U.6,5, function Table adapters 9 11.6.6. Other adapters v 10
TECHNICAL DESCRIPTION OF THE ENIhC, P*RT II.
This part of the report describes in some detail the circuits used in the vcrious units of the ENIAC. Only sufficient programing details, that is, switch settings and plugging details, will be given to enable the reader to understand the circuits. For more detailed programing and illus- trative set-ups the reader is referred to the corresponding chapters and sections of part I of this report.
I. GENERAL DESCRIPTION OF THE EHIAC
This chapter describes the arrangement of the units of the ENIAC, gives a summary of its mode of operation, and describes certain vacuum tube and circuit arrangements which are used repeatedly in the units of the ENLkC. 1.1. Brief description of the ENIAC.
The ENIkC is an extremely high speed electronic numerical computing device. It performs seouences of computations (without manual attention ex- cept for setting up) which are made up of the following operations*
1. Reading initial data from IBM cards
2. Addition
3. Subtraction
4. Multiplication
5. Division
6. Square-rooting
7. Looking up function values in function tables
8. Punching the results on IBM cards.
Generally, the units of the ENI^C have been designed to carry oa the above operations using ten digit decimal numbers. In case greater accuracy is desired provision has been made to carry on the above operations using twenty digit decimal numbers. Actually there is an upper limit to the number of different steps of computation that can be performed without the attention of the operator, but this upper limit has been made high enough to handle a very large class of computing problems.
The ENIAC is a discrete variable rather than a continous variable device. Consequently, errors in computation arise only from mathematical considerations (such as truncation, that is, the replacing of derivatives by difference quotients, jid rounding-off errors) or from failure of some circuit in the device. Careful ittenticn was given to rdnimizing failures and for
1-3
isy location and repair of th-?nr when they occur. The ENInC uses the ecimal system, and handles negative numbers by cscans of complements with espect to 10 . l.l.l. Units of the ENI*C
Table 1-1 gives a list of the units of the ENIhC, the number of program controls of each, '-nd the purpose of each unit. Essentially, the number of program controls determines how many tines that unit may be used for a different purpose in a particular sequence of computations.
The Initiating Unit. Besides a hum oscilloscope to check the a-c supply lines and voltmeters to read the various a-c and d-c voltages, the initiating unit has the following switch controls*
1) Start Switch - Turns on the cooling fans and the heaters. The amber light indicates that the switch h?-s been thrown.
2) D-C On-Off Switch.- This switch is located on the fuse panels. It con be used to turn the d-c power on and off.
3) Stop Switch - Turns off all the power.
U) Initial Clear - Clears all the units in preparation for starting a sequence of computations. Green light cones on when initial clear has occurred.
5) Door shunt switch - Enables the ENI.tC to be operated for checking purposes with some of the back covers off.
6) Reader St?rt Switch - Causes the IBM Reader to read a card and then give out a program pulse which ccn be used for starting 1 sequence of computations. The Reader can be caused to operate by a program pulse rs well as by use of this switch.
7) Initiating Pulse Switch - This switch" causes a synchronized program pulse to be given out. This can be used to start a sequence of computations.
The initiating unit contains selective clear program controls by which certain predetermined accumulators can be ccuscd to clear. The printer program controls are also located in the initiating unit. A clock which acasures the time the power supply heaters ore on is als located on this p^nel.
Cycling Unit. This unit produces the pulses which are used to rep- resent digits or progr-i.. sign' Is, and cruses the various units of the ENLX .
TAELE 1-1 Units uf the ENLX
Nunber Name Mumbcr jf of units of unit ; pr>gr3m ! controls ; per unit
Purpose
Initiating > 6
unit ;
Control center for starting and stopping coir.puti.ti ens. Contains six selective clear j program controls .
Cycling unit
Pulse and gate producing unit which causes the othv.r units of the ENLiC to operate in
synchronism.
20 ■ «ccumula- ! 12 tor i
£ach accumulator con st ;re ten digit numbers,1 add numbers (transmitted by other units) to . j its contents, or transmit its number and/or , its c ■■npl'-i.-a: nt tc other units and clear.
High-Speed ! 2k This unit makes use >f built-in multiplica- ! Multiplier ; | tinn tsbios to perform high-speed raultipli-? . I cation. "
Divider- Square rooter
11 This unit divides two, ten or twenty digit i numbers :nd extracts the square roots of ten or twenty digit numbers.
Function table
11 These units can look up the values of
I functions. The values of the functions must , be set up on switch panels by the operator.
1 I Constant
J Transmitter j ; and IBM reader I
I Printer
] and
j IBM punch
I
This unit reads initial data from IBM cards, sets it up on relays and transmits it electronically. The IBM reader program c ontrol is locrted in the initiating unit.
This unit causes tto~ results of sequences of computations to be punched on IBM cards. The IBM Gang punch program control is located in the initiating unit. :
1 j cluster
: programmer j
This is a pr-gram control device which decides when to change from one sequence if | computations to another, or when to print and when to read more initial data.
Progrim trunks and c'igit trunks
These are transmission lines which make it possible to tr nsfer numbers and program signals from unit to unit as needed.
1-5
to operate in synchronism. Table 1-2 lists the kinds of pulses and gates that are produced at this unit sad tr .nsnitted to the other units over the cycling trunk.
Accumulator. Depending upon the switch settings, digit trunk connec- tions, and program trunk connections an accumulator can accomplish the following things:
1) Store a ten digit number or its complement rmd a PM indication determining which it is.
2) Transmit over a digit trunk the number, its complement, or both. jvftcr transmitting it nay or may not clear as desired,
>) *dd to its contents a positive or negative number transmitted by same other unit cf the ENI^C, properly indicating the sign of the sun.
U) "11 accumulators n-.j transmit their contents by means of static cables to either t*K multiplier or the printer. Certain accumu- lators are semi-pemon-.ntly connected to the printer. The sign indication is transiJLtted to the divider in this manner.
Multiplier. The multiplier multiplies a ten digit nultiplicjJid b7 an n (n«;10) digit multiplier in n*U addition rimes ana rounas of a* the answer to any prescribed number of places if so desired. To do this, the multiplier makes use of four or six accumulators. This high-speed multiplication is accomplished by means of built-in multiplication tables.
Divider-Square Rooter. This unit can divide ten or twenty digit numbers and can extract the square not of a t:n or twenty digit number. If p is the setting of the places switch a division takes 10 ♦ 2 (number of trial subtractions) ♦ 2p addition tines.
Function. Table . The function table working in conjunction with either a variable or a permanent table c^n trsnsroit any one of 104 values of a function (or if less th- n seven digits is needed 208 values of the function). To facilitate interpolation, arrcngcaent has been made to transmit any one of the four neighboring values if desired. If a functional value is to be trans- mitted r tim^s (l$;r ^9) the process .i obtaining th. functional v llue takes
1-6
T*BL5 1-2
Remarks
Kind of pulse or gate
CPP Central Progran Pulse ! Used as a program pulse,
1DP Tens Pulses
j Used to cycle the decades at accumulators when . ; trrdismitting ?. rnr,;bur over the add or subtract ; j outputs.
9P Nines Pulses
! Various combinations ;f these pulses are used I to represent the dibits 0, 1, . «., 9.
j IP 1 2P
1 ,P
U P
One Pulse Two Pulses Two-primed Pulses Four Pulses
*>. oded system n?kes use of various combina- ti ins of these groups to represent the digits 0, 1, 2, ..., 9.
1*P One-primed Pulse
CCG Carry-Clear Gate
' Gener lly used ?s a correction pulse in taking J '. complements (negative nunbers).
Used to tc-kj care of carry-over in the decades j of the accumulators and to clear accumulators : when s^ programed.
RP Reset Pulses
Those pulses are used to reset decide flip- floDs in the accumulators .-nd to provide tht delayed carry-over pulse.
The time unit of ,poratijn for the LNL.C is om= addition time. This is nomally a tine interval of 200 micro-seconds, /.n addition time is divided into 20 pulse tines. e:.ch 10 micro-seconds long. The pulses listed in the above tible arrive via the cycling trunk at oach unit of the EHI»C once each -dditi n tine, Tho pulse tln^s -t which the various puis- s -nd g?tes are produced i3 illustrated by PX-9-301 r by tho dirgran appearing >n the front p^ncl -f the cycling unit.
I -7
* ♦ U addition tines.
Constant Transmitter *nd Eg Reader. The IBM reader con read sixteen groups of positive or negative five digit numbers fr-.ia an IBM card and cnuse these to be set up on relays in the Constant Transmitter. F^ur other gr-ups of five di^it numbers nay be sat up en panel three of the C nstant Transmitter. Provision has been made for combining these five di^it grjups to make t,r •'■j--Ht groups. ":<hen desired, the Constant Transmitter c--n transmit any f these groups :f mr±ers to various >ther units of the EITLiC. Transmission of a number by the constant trr-nsnitter takes one addition tine, but reading and setting up relays to ch&nge a nuriber takes longer.
Printer and TEH Gang Punch. The printer can be connected by static c--bles to eighty decades (and sixteen ?M units) located in either accumulators or in the master programier. './hen so programed the printer will cause the 151 punch tc punch as many as eighty digits (again associated in groups ~>f five ;r its multiples for PH purposes) and 16 PLI indications on the IBM card. Thus, the numbers registered in these printin.- r-ccunulators r in certain dec-.des 3f the iivster Progfsaner cube punched on an IBM card.
Master Pr jgracaer. Mile sequences f computations can be arr nged lcally, th_t is, by setting switches and pluggir.r c:bles :.t the various units of the ENI..C. The master Drogranaaor is particularly designed t? cause certain sequences . f computations to repeat, jt to keep tr: ck >f h r-w n Jiy scquances :re performed, r by ;i£r.ns ,f ^igit r sign c-ntr 1 t:- change the sequences when variables reach prescribed values, jt c .a\bin' ti .ns f these operations. 1.1.2. Digit Trunks.
-v diijit troy i3 about eight feet long and has eleven lines. Ten >f these lines carry the pulses repr-. senting the ten different digits of a ten licit nunber u\d the eleventh carries puis s representing the PM indication.
1-8
takes several trays to extend around to the v.-rious units. Several trays onnected together with jumper csbles and with one load box plugged in forms digit trunk. These digit trays rest on brackets Just above the front panels of the units.
1.1.3. Program Trunks.
Program, trays are similar to digit trays except for the type of outlet sockets. Sever?! trays interconnected with jumpers and one load box plugged in constitute a program trunk. The program trays rest below the front panels of the units.
1.1.4. Static Cables
Vfoenever the decides of an accumulator nre connected by static cables to some other unit it means th: t svery stage in every decade and at least one stage of the Pal counter is connected to the proper points of the other unit (printer, for example). To accomplish this, two 55 conductor cables en used. In the case of the accuraul'.tor to printer connections, only 51 leads of each c^ble aro used, that is, 50 for five decades and the other line for PM indication. «n adaptor is used at the accumulator end to connect both Pil lines to the U static output of the PH counter. In the case of the static connections to the Liist<-r Prcgrrnner the P*i line is not used, but an •daptor (see 9.2) must be inserted in the printer to kticp the P2J rd :ys from operating. 1.2. FUnK'tLUT .J. LLECTROBIC UKETS OF 7HL 3JLX
There re certain fundamental circuits which are repeated many times throughout the ENL-C. V7e sh'-ll discuss a number of thests here. In the course of the following discussion we sh-.ll use the terms "pulse" and "gate" with the following meanings:
Pulse i •» pulse is 3 positive or native change in potential which has a duration of ?.beut two to five micro-seconds (usee.)
1-9
Gate, a gate is a positive or negative change in potential which l duration of ten micro-seconds or more. The Carry-Clear Gate (see -306), for example, lasts for 70 micro-seconds.
It will be seen that the same type of electronic units located in ?erent parts- of the £NIhC operate at different absolute voltage levels. For example, tho flip-fl^p illustrated (PX-1-105) operates in a voltage range m -555 volts t» -360 volts. Other flip- flops operate in ranges of from -85 +110 volts and from -920 to -725 volts. The power supply produces a range P voltages from -920 volts to *550 volts.
Throughout this report the following convention will be followed with gard te input and output circuits, *n input or output will always be rep- resented by only one lead. The return circuit should always be thought of as ~oing back to some point on the bleeder of the power supply. For example, the cathode of a tube may be at zero volts and the output may come from the plate with a range of potential of from 100 volts to 150 volts, say. Instead of using this output with respects zero it may be used with respect to -20 volts giving an input potential for the next circuit of from 120 volts to 170 volts. Thus, the reference point varies a great deal from circuit through the ENIaC.. and it seems impractical to try to represent the return circuits on ruch diagrams as FX-1-105 to PX-1-110. 1.2.1. Flip-flop.
k flip-flop is a four tube vacuum circuit which is the electronic analogue of an electric switch. Two of the tubes (T3and T^ on PX-1-105) constitute the flip-flop itself, that is, a circuit with two stable states. The other pair of tubes (Tj_ and T2) are called triggering tubes.
The triggering tubes, assuming that no signal is arriving over the set input, the grid of T, is at saturation. This causes the tube to conduct. Thus, if a negative signal *f the proper magnitude arrives over the set input the grid will fall below cut-off and the tube will cease to conduct.
I - 10
In order to secure reliable operation it has been a design principle
hat in all such cases the grid should be driven three tines below cut-off.
orthemore, to provide for the increase in tube resistance with aging, the
pplied signal has been so arranged thct it will always be ?t least two and
ne half times below cut-off.
The flip-flop. If the trigger tube T <?oes off the grid of T will
^ise well shove the cathode potenti:l anc T will start conducting. The plate
potential of T^ will drop and this drop in potenti-1 will be carried through the
condenser C, to the grid of T. tending to cause T. to go off. As T. starts to U U 4 4
^o off its plate potential rises through condenser C_ this causes the grid of
To to rise even faster. Thus, the whole process accelerates. Tube T becomes
conducting and T, goes off. This being a stable condition, the tube To remains
on and T off until such tira^ as triggsr tube T goes off. 4 2
The output potenti-.l -t 0, is -490 volts and of 0 is -430 volts. After the flip-flop is set by an incoming signal ct S the potentials of 0, and Op are irrtrerch->ngud, and they will rom:in this way until a r set signal arrives t at R.
Note that the condensers C\ and C„ isolate the DC circuits so the input to the flip-flop my operate it a volt ge level which is sometimes as much as 600 volts above the leval of th> flip-flop.
The general pi n will be to connect the outputs 01 :nd 02 to the grids of tubes whose cathodes re -t a potential between these two output potentials. For ex-mplc, in receivers nd tr: nsc ivers th.s~ outputs go to th grids of 6SN7's whose c-ithodes -re at -450 volts. Thus, -490 volts is well below cut- off for the one tube where: s -430 volts is far bov^ cut-off for the other one. In this n-.nner st:itic volti-gcs produced by ; flip-flop ar - tr nsmitted to other circuits.
The n^cn light is visible on th- front ptncl. It is lighted wh^n the flip-flop is Sit, th t is when tube T.. is conducting.
I - u
2.2. Counters
M Counters. The Pal counter is => binary ring counter. That is, has two stable states -nd just one input line, h first incoming signal Ml step it from stage one to stage two whereas the second incoming signal '.11 step it b'-ck to st: ge one. Thus, an ev-.n numbor of pulses arriving over he input line will leave it in its initial condition whereas sn odd number leaves, it in the oth^r state.
The tubes T. end T2 in PX-1-109 act ?s triggering tubes. Whenever at positive signal arrives on the input both of these tubesA begin to conduct. This causes th ; grids ->nd pi: tes of both T_ and T to tcke a negative swing. Since T^ is off it has nc effect there, but To is caused to go off. As To goes off its plate becomes more positive End through condenser C, the grid of T, also tc-kes a positive swing, ks T begins to conduct its plate takes a negative swing and this through condenser Co further cuses tube To to go off.
The strtic output circuits are Mtjey simile, r to the outputs of the flip-flop described above. The positive output has the high potential (relative to the other output) whenever the Pli counter is registering a positive number. With tube T conducting ind T not (us illustrated) the neon bulb labeled P will be lit and the on.- 1: b-led 11 not.
a counter simiL r to the PM counter is used in the divider-square r»oter.
Decade ring counters, a dec.-.de ring counter is a ten stage (with two tubes per st::ge) ring counter with ten different st-ble states. Each st- ge has two tubes which will be called respectively tube I nd tube II. Only one tube of e ch st g- is conducting. If tube I is conducting th t st ge will be s id to bo in st:te I; if tube II is conducting th n that will be s_id to be in state II. The st-ble state of th. whole ring is with one st-gc in st.te I .nd th, other nine st- ges in st'U II. Thfe circuits (sec the cross
1-12 tion PX-5^115 or the decrde wiring dirgram PX-5-133) ape so arranged that one stage is in st*tc I ~nd . puis 3 is received it will go into state II nd - next following stage will go into strte I. Pulses th t step the ring are jative and re introduced en "11 thi c thodes of the tubes II. This pulse has ttle ..ffoct on th- strg^s in stjt<- II but c us--s the stage in state I to go to st:te II. as this stfge goes from state I to II the cirry-over circuit uses the next following st-ge to go into st?te I. The fact that this carry- -er pulse (through the 50 pf . condenser) will be in conflict with the stepping also -ppliod to th c'thode requires c-roful design to obt: in reliable operation, ~hus, the stepping pulse must be of precise shape and dur-tion, and the c" rry ver pulse must _ver-ride it. This is accomplished by putting the incoming julses through a pulse stenchrdizer (s-e section 1.2.7.) ^d" by using the proper circuit prr;mcters in the decade ring circuit.
The two c thode resistors for tubes in st? te I and tubes in state II are so chosen to permit only one mode of operation, miiely, one stage in stcte I and the other nine st: ges in st'te II.
Other ring counters. There are i number of other ring counters in the various units of then ENIaC. Essentially they differ from the decide ring counters only in the number of st- g.s they contrdn. n list of these ring counters follows:
a) The r3p-^tcr ring. (See PX-5-115) The repeater ring is used in each _ccumul"tor to count the number of times a particular rcpect program control operates. This ring nd its pulse standcrdizer -re built in one plug-in unit. This s'me plug-in unit is used in the Divider-Square rooter for a different purpose, see (d) below.
t) The cycling unit ring. (See PX-9-307) Th.re is :, twenty stage ring count-r in the cycling unit which controls wh.t happens during the twenty pulse times of -n 'ddition time.
1-13 e) The multiplier ring. (See PX-6-306) This ring controls the :ess of multiplication. It consists of fourteen stages, ten of which are oeiated with the ten digits of the multiplier which may b« used in multi- '. cation.
d) The divider-squrre rooter program ring. (See PX-10-30utO This ag controls the b -ginning and fiir-1 p'rts of the processes of division or
mare rooting. It is a nine stage ring which with its pulse stundardizer is entical with the repeater ring plug-in units, (see a) above)
e) The divider-square rooter place ring. (See PX-1D-304) This :n stage ring keeps track of the pl-ce in the division op square rooting -ocoss. This ring is identical with the master progrMxior decade rinss
(see i) below).
f) The function U-ble argument ring counters. (See PX-7-304) These rings (a units ring of ten st.ges :nd -a tens ring of eleven stages) receive the argument from an rccumulatar.
g) The function table program ring. (See PX-7-3Q4) This thirteen -?tage ring controls the setting up of the function table networks and counts
he number of times (up to nine) the functional vi-lue may be transmitted.
h) Master progr-.mor dec:de rings. (See PX-8-304) There are twenty decade rings located on the two p'-nels of the master programmer. These can be used to count the number cf times certain sequences of computations ore performed.
i) Li- ster progrrmcr stepper rings. (See PX-8-30/*) There are ten six stage rings which =re associated with the ten steppers of the master programmer. These control the output of the progr m pulses given out by the master orogrammer. 1.2.3. G-te Tubes.
Besides being able to count ^nd record pulsus at high r tcs it is necessary to control the puis s, switching them into ont unit or .mother. . :.
I - u
In order to do this ouickly, electron!* switching is used, a vacuum tube used as a switch so as to ~llow or deny passage of pulses or other signals is known as a gate. Gate tubes are used in the ENIAC for a variety of control purposes. They connect the inout channels of : ny given accumulator to particular digit tr.ys when desired. They are used in thy carryover circuits to pfss cirry over pulses. Eoch programming circuit contins many gv.te tubes.
iiost of the gating or switching in the EftLiC is accomplished by the use of multiple grid vacuum tubi.s. Various gate tube circuits are illustrated on di- cram PX-1-106. If there is no inpW. signal to either control grid of the gate tub- of PX-1-106, the second control grid is at ab.ut -Z^Ov* This is well belov cut-off for thr.t grid (cut-off is -14 volts for 6S*7 with the first control grid connected to the c'thodo). Moreover, the first control grid is at -40 volts which is well below cut-off (-7 volts if second control grid is connected to the c-thode), so the tube is not conducting and the potential on the output is ne:r -+160 volts. If any positive signrl (of about 50 volts) arrives on either control grid the tube will not conduct. Thus, any signal arriving on the first input has no effect. However, if a signal arrives on both grids the tub-"? will conduct and the plcte potential will drop. For example, input 2 may connect to the pl-te of an inverter tube (see section . 1.2.6.) which is normrlly on. If this inverter tube is conducting and the circuit parameters ..re properly arranged the potential of control grid 2 will be well below cut-off and ^ny signal arriving on control grid 1 will not be p-.sscd. .b-n th< inverter is off the second control grid is at about *20 volts • nd any positive: signal 'rriving : t the first control grid will be passed.
The resistance .nd voltages • nd even the- type of tube used in g- ting circuits vrrics from circuit to circuit throughout the ^NI^C. Various situations are illustrated on th. cross sections of the units of the ENI*C.
rt gate tube may be died a coincidence tube, since an output will be obt .ined only if th.. signals -ppliod to the inputs one and two coincide in
1-15 time. Two other types of coincidence circuits used respectively in the Function Table and the klasttr Progranmer art. illustrated on PX-1-104>.
In the case of the triple coincidence circuit r-11 three of the tubes 1, 2, and 3 must go off before the tv,o control grids of the 807 (tube U) are sufficiently positive for it to conduct. In the Master Progrrjnner circuit any one of the tubes 2, 3, U, 5, or 6 being on is sufficient to hold the second control grid potential below cut-off. Thus, the g^t- (tube 1) will conduct only when then, is 3 positive signal on th~ first input and the five tubes (2, 3, 4, 5 and 6) are off.
The positive grte potentials which must be supplied to a g_te tube for switching purposes can be obtained from the outputs of a flip-flop (see section 1.2.1.). Y&th the proper rel_tionship of supply voltages for the gate tube and the flip-flop one of the outputs of the flip-flop may be con- nected directly to one of the control grids of the gate tube. Th^ effect obtained is that of a switch which nuy be opened or closed at desired times by pulses applied to the S or R inputs of the flip-flop.
As a matter of policy the grids are driven to saturation when the tubes are on and they arc three to four times below cut-off when off. This means the circuits are not -mplitude sensitive, that is, a considerable change in supply potentials and in tube conductance (due to ?ging) will not effect the reliability :>f operation. Furthermore, to avoid coincidence problems pulses are never used to g".te other pulses; th't is, .-t least one grid of a gate tube is always operated by a gate voltage. 1.2,4* Buffer Tubes.
Many occ sions arise in which it is nccess ry to couple two or more circuits, say, *, B, C, etc., to another circuit, X, so that any one, say a, can operate X without affecting th others, B, C, etc. This can be done by the use of buffer tubes :s illustrated m PX-1-107. If such a tube has its grid beljw cut-)ff then my ch np;e in pit- potential will not c -use any disturbance
1-16 in the potentials of the grid or tethodfe circuits. Thus, the plates of a number of such tubes (representing the circuits A, B, C, etc.) may be con- nected together to the input of the circuit X. If the grid of me of these buffer tubes receives s positiv. signal the tube will go on causing a negative input signal to circuit X. This will c-use no disturbance in the grid potentials of the tubes which do not go on. On the other hand no harm is d^ne if more than one buffer tube goes an,
a good illustration of the action of buffer tubes is given on f.ie accumulator cross section PX-5-115. There are eight clear gate buffers (CL. G. B., tube 63) with the plates (CBjO all connected to the grid of an inverter tube (J50 in the gate unit). If any one of these buffers begins to conduct the potential on all the plates end on the ^rid tf J50 will fall. The only effect will be that J50 will go off. Although the grids jf these clear gate buffers are directly connected tj the gate tubes 68 in the transceivers, these gates are n * disturbed in the other seven transceivers.
1.2.5. Cathode Followers.
k c.th.de follower is illustrated on PX-1-107. The input of this tube is connected to the plate of an inverter tube which is normally on. This holds the grid potenti: 1 >f the cathode follower bel^w cut-off. If s signnl turns this inverter tube off the grid will rise 1 1 about 50 *olts and the csth-^de follower will ber-in to c induct, .^.s the tube gees on the cathode will rise in potential riving a p sitive utput. This rise in potential is limited by the grid pot> ntial.
Thus, in the c?se f a cathodi follower s p sitive input gives a positive output.
1.2.6, Inverter Tubes
If a p. sitive pulse or g'te, rather than •. neg tive one, is required (in rder tj per:te not her R te tube, for example), th^n an additional tube must be insert ori in the circuit. This tube is known as an "ir.verter". It is
I -IT
normally conducting, and when a negative potential is applied to its grid, »o as to bias it to cut-off, ?. positive chonge in pl«?te potential takes place. This may then be used to operate ;th.=r tubes, normally non-c inducting in the desired way.
The role o£ a- g^ix tube is, that of the logical "and" while a buffer is similar to a logical "or", arrangements of inverters such as illustrated on PX-1-10-6 also corresponds to the logical "and", 1.2.7. Pulse Standardizer.
It has been mentioned thr.t in the operation of a counter it is necessary that the input pulses have a certain shape and magnitude. Dis- tortion of pulses because of the capacitance of interconnecting circuits and because of passage through various gate tubes makes it necessary to use pulse- standardizing circuits at the counter input to secure reliable operation. The pulse standardizer circuit includes a flip-flop different frjn that discussed in 1.2.1. in that one of its states is only semi-stable.
After an input pulse has flipped the circuit, it will flip beck to its original state in a time determined by the circuit constats and practically independent of the input pulse, (See PX-1-110).
The explanation of this action is as follows* the v lues of R , R,,
and R- are such th -t when tube T_ is conducting, the current through Rz biases
tube ?2 to cutoff. If a negative pulse is applied to the input, T^ goes -.ff
and tube T2 is turned on, and the voltage ?t the plate f tube T2 drops because
of the current through R, . This v>ltage drop is transmitted to the grid of tube 4
1-i through the capacity C,, and tube T_ is thereby cut >ff. However, this negative bias is gradually lost because current then flows through R? to the grid ?nd the capacit.-r C., therefore after a time which depends >n the pr:duct R-jC^, tube T is n> longer bi-sed t > cut-off; ond as it begins t ; conduct, the increased current through R, begins to bias tube T2 to cut-"»ff again. This change in tube T2 rects n tube 1y and the actien is accelerated, flipping
1-18
the circuit back t > its riginal state.
When used to supply pr perly stuped pulse to a c mnter this
circuit includes a p-.wer -utput tube, T .
U
Special pulse standardize^ - diagrrjn zt the special pulse standr<rdizer appears on PX-1-110. Tta diagram. sh;ws a switch on the input* actually, there are three of these circuits all 1 ;c-ted in the cycling unit (see PX-9-307). nd the respective inputs c:me from (*.) the initiating pulse switch on the fr^nt p ,-nel ,f the initiating unit, (b) the reset can of the IBM punch, and (c) from the finish can f the IBM reader.
If the switch is closed the c. ndenser C, will discharge through the A.7K resist jr. The tine c instant for thij discharging acti >n is slightly n-re than 2 milliseconds. Thus, the switch should be closed for a period A at ler.st this many milisecwnds, «s the condenser discharges the grids -;f tube T. dr^p in p tentic 1 and the tube goes off.
After the switch is opened th^ time const. -nt f ->r charging is about 50 milisec nds. Therefore, if the switch were pushed again before the c ndenser had recharged, th<; tube T, would h?ve not began to conduct again and there w,uld bo n;> .utput pulse th^ second tine. The tine constants here are purposely sl>w (c-rapored t the. speed ~f • pcr=~ti n f the EIIIkC) to prevent any chatt .ring f the c.ntacts -f the switch (or ther transient effects) from causing n.re than one pulse t be given out.
rtS tube T. g;es off its plate potential rises causing tube T2 t.
c.nduct. The flip-flop action of tub;s T2 nd T-j giv^s a negative pulse to
the c ndenser C causing the tube T^ t: g; ff. Aether T2 remains off ,r
n.t (it wiU remain iff ;s long as the switch is cl sed) the grid >f T^ will
chrge up thr -ugh the 160K resist rs cusinr the tube t c nduct again. The
tine that tube T is ;ff is, theref re, independent f the length v.f time thrt
4 thv switch makes contact. N.>te th^t rele-sing the switch causes T2 t. g off
1-19 giving a p-sitive signal througfi the cndenser to the srid of T, . Since T, is already conducting this positive pulse h.s no effect. 1.2.8. Transmitter
PX-1-108 shows the details of a transmitter circuit. Because of the large cspadtrnees associated with the interconnection circuits, such as digit trays, program trays, ind patch cords, it is necessary to use power tubes working into relatively low la _d resistances in order to transmit pulses from one unit to another at the rate of 100,000 pulses per second. Th^se pulses are positive in order t ; operate gate tubes and buffer tubes in the accumulators. The diagram of PX-1-108 illustrates the method of achieving this.
The output, or transmitter, tubes have a low resistance in the cathode circuit, 220 ohms. This lead resistance is located in a load box tnd is plugged into a socket in the digit or program trunk into which the trans*- mitter output' is fed. . The lo~d. resistance cannot be connected permanently to the cathodes of the transmitter tubes. since depending ;upon the jumper connec- tijnd.made on th3_front panel sever_l transmitter tubes may feed into the same line.. -Thus, just one load box must be plugged; into, each digit^and each program trunk, :• '. - .. ?l * . i< c :• ;•■ u c:c .t., s.cv.
The transmitter tubvs <.r- normally ..ff.- Since the output load is.- essenti lly a largtirc~p«cit nc.-, the positive pulse can be produced quickly only by driving th<, grids f. these output tubes. positi ve ;with respect to, their cathodes; In order to oaks the mtput pulse amplitude stable, i the grid must bo sufficiently positive so as to. re^ch the saturation current for the tube. Considerable grid current will then flow, and it is necessary to pro- vide another tube, known as the drivertubc, capable jf. maintaining the re- quired grid -potential under these conditions. The driver tube is actually a smaller power tube. It is normally conducting, and is cut off by a negative pulse .-input tj its grid, r et. .;
1-20
When a signal rrrives at the driving tube the grid drops from about -105 volts to approximately -I65 volts. This causes the driver tube to go off raising the grid potential of the transmitter tubes, na the trans- mitters-go on the cathode potential rises to about 45 volts.
The digit outputs of the divider end multiplier do not have standard transmitters. They have inverter tubes with built in load resistances. Thus, the lines that these tubes feed into must not have load boxes and f-Jt reliable operation the pulses should not be fed into a transmission system exceeding t<v loading rules stated in the operator's manual. 1.2.9. Receiver Plug-in Pnlt;
The wiring details of a receiver appear on the accumulator cross section : (PX-5-115 while a block disgram representation of the receiver appears on PX-5-304 ( accumulat )r block di .gram). For a detail wiring diagram of a receiver plug-in unit the reader is referred to PX-5-148.
The incoming signal arrivos at a buffer (tube 66) turning it on. This causes a drop in the plate p^tentiil, that is, this tube inverts the signal. The negative output of this buffer is used to set the flip-flop (64, 65 say). The positive (that is, positive after initial clearing) output cf the flip-flop feeds into wh: t is called a fsst buffer utput (62 and 63). This is an inverter (62) operating - cathode follower (63). The inverter is normally on. When the flip-flop is set the decrease in potential on the output turns the inverter ->ff and the cathode f ^11 .wer on. This ives a positive gate on the output. The n-rmally ncg.tivc output of th^ flip-flop goes to a buffer tube (62) forming what is colled the slow buffer output. The time constant for this output is much longer than that of the so c lied fast buffer outputj this explains the terminology.
Tha negative utput •>£ the flip-flop also goes to the grid of a gate tube (61). iVhon the flip-flop is set this gate can p.ss a reset signal causing the flip-flop to reset. In the case ~f receivers used in the accumu-
1-21
lators the other grid af this gate is connected to the central program pulse (CPP) line. Since the set signal is usually a CPP gated at some other unit af the ENIi.C the receiver «Ul start ta come on at about pulse time 17 (or slightly later depending upon tho time constants of the intervening path) cf one addition time. *t pulse tine 17 of the next additi -n time the reset gate (the time constants are such that this does net open in time to pass a resetting CPP which would conflict with the setting program pulse) pass a CPP which resets the flip-flop. Thus, the receiver is on for one addition time. In other units (in particular, in the divider and multiplier) the ivset pulse passes through other gjtes which allow the receiver to remain on more than one addition time. 1.2.1Q. Transceiver Plug-in Unit.
*a with the receiver the wiring details cf a transceiver appear on the accumulator cross section PX-5-115 snd a block diagr ja representation appears on tho accumulator block dia,.?ram PX-5-30A. For a detailed wiring diagram tf a transceiver the reader is referred to PX-5-147.
as fir as the fast buffer output is concerned the transceiver is identical with a receiver. On the normally negative output of the flip-flop are two buffers (61) giving two slow buffer outputs. This line also feeds a reset gate (62). The ..utput of the reset gste goes through an inverter (65) to two more buffer outputs (63) and to a gate (68) which passes a CPP. The CPP possed by this gate resets the flip-flop nd goes through a transmitter.
The usual mode of operation is as follows, nn incoming program pulse goes through a buffer (69) and sets the flip-flop. The gates provided by the f^st end slow buffer outputs are used t: cruse the unit to perform a cort&in task. V."hen the task is finished a sijn.'-l arrives at the gate opened by the normally negative (now positive) output of the flip-flop. The g&te passes this signal turning off an inverter giving tw m ;re -.utput gate signals
1-22
i
and opening another gate to pass a CPP. This CPP resets the flip-flop and
is triinsnitted (via cables and program trunk) to sone other unit to program the
next step in the computation. The delayed buffers (63) furnish gate signals
which nay perform the fin-:l p*rts ~f an operation such as the case of an
aceumlator.
1,3. BLOCK *SD CROSS SEjCTION DI..SUiS.
Chooters II to X are derated tc descriptions of the various units of the ENL.C. The descriptions of the units will, in general, be given in terns of block diagrams and cross section di- grans, n. block diagram uses circles and rc-ctengles tc represent various electronic devices, and has the f-jlljwing purposes:
1) tc aid in understanding the various circuits and their operetion without going into details.
2) t j enable people with computational problems to understand the ENL.C sufficiently (irrespective of their electronic background) so as to &dapt their problems to it.
3) to assist th-j maintenance nan in finding mechanical and electrical failures,
Crss section diagrams give typical circuits in all detail, that is, all resistors, condensers, inductances, tubes, all voltcges, et cetera, are given. If a unit c ntuins many circuits which are pr- cticrlly identical, only one appears on the cross section. The cross sections have the following purposes;
1) to enable the pers »n with an electronic backgr >und to understand in detail how the LKUC operates.
2) to assist the service nan in asking proper replacements of parts. »s a general practice in the f. 11 wing chepters, programming details
(switch settings md plugging f interconnect rs) will be described only to the extent required to understand the circuits. For n re detailed programming and
1-23
illustrative set-ups the reader is referred to the corresponding chapter and sections of part I of this report.
As standard prectice on all block diagrams the following c-nrenti-ns will be followed:
1) Broken lines indicate pulse carrying lines while solid lines carry gates.
2) Tubes (except for stages of rings and pulse stijidardizers) which are normally conducting are shrded, ethers not. The word "normal- ly" litre means immediately after initially clearing, or in the case of the cycling unit, the situation which exists when the ring is at stage zero and nr; pulse is coining fr-aa the oscillator.
3) Plug-in units will be represented by rectangles with heavy borders.
II (1)
II. miTLiTKG UNIT
The initiating unit, as tire name lilies, contains the control * -which start and stop (turn on and turn off the pewer) the EjJIaC. There is a push button on the initiating unit front panel (see PX-9-302) which initially clears the EITlAff, that is, it clears all decades to their zero stage, clears Pi; rings to their first (?) stage, repeater rings to stage ono, and program controls to thoir unactivatod stt.tc, and so forth. Tho program terminals and controls for the I3Ii reader and punch arc located on this panel. From theso controls program pulses can cause the reader to read a new card, or the printer to print the- :mmvers registered in certain accumulators and possibly sar. a .caees of the mast.r programmer. Also there is a push button by which the r-.ei_r cay b^ caused to read a n-'.r c-rd. '"hr.i til. curd reading is finish d and an interlock signal has arrived, a progr.-m pulse is giv~n out from on^ of thv. terminals on the front p-jiel (s „ PX-9-302, terminal HQ). Th_ interlock signal is a progr:ja pulse indicting th^ Z,lil.£ has finished som~ oth-r sequence of conput.-tions which was going on simultaneously .rith the card reading. In manual operation, by the push button, no interlock signal is needed. Likev/ise, when the printer relays have set at the beginning of the card punching cycle a program pulse is obtained frou a terminal on the front panel (terminal FQ). These pulses can be carried over lines of a pro ram trunk to some oth.r unit of the 2:LX, causing cone other opera- tion to take place. There is another push bat- on which producs ^rhat is called an initiating pulse (at t~rmin.-.l ij that can be used similar- ly to the reader _and_ printer pro~r._- output puis -S. There er. six
II (2)
program input and output tcnaincrls (Cj and CQ on PX-9-302) associated with six transceivers which trans .it the selective clear gate over the cycling unit trunk. This s. Active cl.ar gate (3CG) goes to each of the twenty eocuuulators and causes those .rhich arc so s.t (set to selective cl.ar) to clear. Th,.r; is anoth-r push button which shunts out the door switches and allows the E. I.£ to be operated with the doors of some of the units off, this is cdled thu door switch shunt.
2.1 STr-RTLIG ^ilS STOPPING oEiUENCE .-^:D LUi"lAL CLE«R
The following descriptions will bo given in terms of diagrams PX-1-101 (Power and control wiring for the ETJLiC) and PX-9-307 (Cycling unit and initiating unit block diagram). The right hand portion of PX-9-307 shows the circuits located cither in the initiating unit or on the switching and fuse panels. The left hand portion shows the circuits of the cycling unit. 2.1.1 formal Initial Conditions
The normal state with th- EUL.C turned off is to have relays . C and II (s,e the simplifi.d control circuits on upper rijht corner of FX-1-101 or s.e th- low..r right h-na corner of PX-9-307) ..ctiv..ted.
In series with relay Z are 46 door switches (shunted out by th- door switch ehunt - sa PX-9-302) , and 43 therr.ost..ts . If any one of these 89 contacts ic open then relay C -.Till b_ un-.ct ivatcd , and , a* explained below, this makes it ia?osciblw to turn the EilL.C on. The theriuoct-.ts are locate in the tops of the v.rious units which contain v:.cuun; tubes. If thvj tomporcture of uiy one of these unite rioos abbvc 115° tho corresponding thermost..t contact will open and turn the EHIaC
11 (3)
off or prevent it fron bwing turn-d on (until tho unit cools down). Vhcn the doors are off of the jacks of tho various units a person is exposed to voltc-ge differences amounting to as much as 1500 volts. Each such door opart. tea a. door sr.itch which v.ill oausa rerlay C to drop out (unless the door switch shunt is operated)
•7hen relay Cj drops out tho P timer starts (this timer may be set to run frcui 0 to 15 minutes before it closes its contact PO. During the period that the timer is running,;, bell will ring to indicate that this timer is about to turn the EUIaC off (if it has been turned on). This turning off is accomplished by pening contact P. which opens the holding circuit cf the auxiliary relay A. This in turn caucus all the contactors and cart.. in auxiliary relays to drop out shuting off all power (d-c <*nd heater) to the EIT1AC.
Thus, if a thermostat cp*ns the circuit, or if the back cover is r:movsd ep=ning u i-or switch {'.ihsn. the doer switch shunt is not operated) the P tin^r starts, a bill rin-s, rend at the end of the period (0 to 15 minutes), all power is shut off free: tile ZiilAC. This time interval gives the cpsr.tor tin- to prrh-ps correct ths fault (for exuaple, check the ventilation system) before ths power goes off. This system is designed to minimize ihi number of time3 the heaters are turned off snd on sinoe this turning eff cna on has been found to cause numerous tube failures (burned oat heaters and hsater-cathode shorts).
The relay II has in serieo with it the power supply heater phase failure rs:l«ys (3 relays), the power supply phase failure rs-lays (3 relays), aid the under volt*e« release relaye (28 relays). All these contacts -J9 cpon vfaKk ths po -er is eff, thus, C cent. -.ct en r*l&y X (ccxt£pt Kg) shunts th?se circuitt until relay * ie activated. Sine* relay K is not i»ctivat#d
II U)
until e. minute and ten seconds after the start button la operat«d or ton seconds after the d-c pcrcar c:u»s en, this »Ilcvrc th. under volt&ga raleas© relr.ys and ths phf^s failure rsltys to pick up. In other w.rds, thjrs is no underv.Itr.gc jr plv.se failure protect icn during this ten second Interval. If there is an undervoltage (because of failure in some porrer supply) or a phase failure, then one of these relays will drop out (or not be picked up .:hen the machine is started) and the relay II will drop out ..-hen relay S is activated. As ^xplaira-d belo.7 xhis will shut off the plati supply to the pov/er supplies, and consequently turns off th- d-c to th>* Z3»LiC. This leaves all the heater voltages on but turns off the d-c.
2. 1 . 2 Complete Starting Secuenco
(1) Fush start push button (on initiating i^iit front panel, PX-9-302).
Relay A is activated (assuming relay C is activated)..
Contactor D is activated by a contact on relay A. This turns on the EIJL-.C heaters picking up the h-ator phase failure relays (6 relays). R*lay a is nor/.- h6ld by contacts F and Bj. Contact or 3 is : <?ld by contacts Aj and Bj.
The start pilot (ar.ber light on initiating unit front panel) and the po.-er supply tiiu-i r^cord^r (on initiating unic front panel, tells totul tine that th: power supply hsatars have bfcon on) are turned on by contact A. on r-;l-y A. If any d-c fucss are bio -sa then a circuit through contact A4 and a contact on one of the d-c fuse relays causes rslay L to pick up. Thic would prevent the d-c powor frorn being turned on by printing contactor G from being activated. If any of tha power supply
11(5)
fila.-n.-nt fuses .-.in. J>lown the relay 3 will pick up and hold on contact <i2.
Contactor £ is picked up by contact A^ oa relay A. This supplies power to the fans in the ventilating cyst am*
Contactor D is picked up by contact E. on contactor 3 (assuming that rslay 4 Is inactivated). This furnieh.-d power to ths power supply heaters.
The- one-minut- timer F is started by a contact D, on contact*-.! D provided hs_t=r phr.32 f&ilure relays have picked up. This timer runs for one ir.inute and then th. con -act lebcllid F, is closed. This contact remains closed r.e long as power is applied to the timer, that is, as long as contactor D is activated. "Thsnev r power is removed the contacts open and the- timer resets itself.
After one minute th_ povrer supply contactor G is picksd up by the timor ccnt.ct Fj (assuming r^lay L is not activated). This contact furnishes pow.r to the plates of the rectifiers in the power supply *nd thus furnishes d-c pow.r to the D1TL;C<
R&l.yc H and I' Jid ths tan second tiu ;r J are picked up by contact G. on contr.ctor G. The initi .1 clc j- relay So. 1 (il) operates Cw-rt..in relays in the initiating unit which proiuos th^ i.iitie.l el-ar gate (ICG) (see Section 2.1.2). Ths 14 under vo It »gc relets, pick-up relays 1. shunt the resistances in series uith the coils of the undervolt..gc- rel.-ase ralays. Sines the drop-out point for <•. relay is considerably bc- lov; the pick-up point ths resistances in series with th. coils art r.e jus ted so th-.t . suf.11 drop in voltage fron era of the ;-cvar suppli s will c.uee the r-l-y to drop out i.i\l thus shut eff the d-c pow.r (by ra- lo sing rtlay V. which ^icks up r.lay L). The- pick-up point i3 then too
11(6)
high for those relays to be picked up by the voltage from the power supplie
Thus, for a period of ten seconds (during the running of the tan smsatd
tfcner) the relays U cause these resistances to be shunted with sualler
resistancss to enable the relays to piek-up.
Ton seconds later the contact J. closes on the ten socond tiner.
This causes relay £ to pick up. Relay £ holds on a circuit through
contacts Gj, E^, and tho initial clear push button. '.Then relay K is
activated, contact K opons, releasing relays E and K, and allowing tho
ticer J to reset. Contact £ opens allying the phase failure and under 2
voltage protection (sinc-j relay r. is also relcas.d). Contact K closes turning on tho ready pilot (green light on initiating unit panel).
The green light indicates that the power is on and that tho S3IAC has been initially cleared (as described in Section 2.1,2) and is r~ady to start cor.pu tat ions. 2. 1 . 3 The d-c off Sequence
Push the d-c stop button. This ceases relay L to be activated. R^-lay L renains activated by circuit through d-c start button and holding contact L2. Contact L opens dropping contactor G. This shuts off tho plate supply to the power supply and thus shuts off the d-c to the ENIAC. Contact Q1 opens dropping relay K (this puts the initial clear circuits into their noraal initiul state).
If a d-c fuse blows, one of the d-c fuse relays will pick up. This will activate r^lay L and h-ve the s-cc effect as pushing the d-c stop button. If the voltage from any one of the various power suppli.s is subnormal, one of the und_rvolt-gc releeao rel-ys will drop out. If th.rc is ;. ph>ec failure in the voltage to either the HTI..C heaters or to
II (7)
the pewsr supply heaters or plater one of the phase failure relays will drop out. In any of these last cases relay X will drop out closing the contact Ij. This, again, has th<= sane effect as pushing the 4-c step button.
Frequent turning off and on. of the heaters of ths tubes is undesirable bee-use this t=nds to incre_se the number of heater failures. Thus,, the &-c on and off circuits arv provided so tiu.t the heaters laay be I^ft on continuously while the d-c c_n be turned off when the machine is not in use or when ports .-zust be rc.ploc=-d.
A locking arrc-ngazent is provid.d so that personnel nay padlock the d-c st_rt ejid stop buttons .nd prcv-nt anyone from turning on tht- d-c while someone is r.oiking on thv n_chine.
Should one cf ths power supply heat r fus^s blow, ons of the thres power supply heater fuss relays will operate. This will pick up relay 2, which by opening the contact ~_^. will turn off all power to the power supply. (Contactor D will be deactivated removing hcate» power. Timor contact P will open sines ccnt<-ct D. has opened deenergiiing timer ?, and he-nce the plate supply throu^i contactor G will also be turned off). *'ith power supply heaters d^n=rgized it is oofo to replace a heater alarm fuse, although it is recjaaend^d that additional precaution be taken by opening safety disc-, nn^st switch which has be«;n provided. If th- safety discc/intct switch is us^d. it gust be again closed before itt.aptijig to turn on th= d-c porsHr. 2.1.4 The d-c on Sequence
Push the d-c st.j-t butt .a. This caus.s relay L to drop out. The d-c cent ct or G is cick_d up sy .. circuit through contacts F^ and L.
II-8
The rest of the sequence is exactly like the l«st part of the sequence described :.bove (see Section 2.1.2).
If the power supply u_c sad d-c has b^en turned -jff front & h;_ter fuse failure, pushing the- d-c stsj-t button v/ill turn it on since, rslcy 5 ./ill be released p.=raitting contactor D tc pick-up through Q,. The rest of the sequence is exactly like ths lr.st pert of the sequence described ?.bove (Section 2.1.2). It "hfculd be noted rhat Khan relay ? trips off the d-c, cm extra one nir.ute (ever & relay L tripping) will el;-.pso bvtwesn the pushing cf the d-c st^-j-t buttcn end the initidly cleared jign'.l since timer F is now introducing tube ..'erm-up delay. 2. 1. 5 Th*. Initial Clear
llcfj the and of th- st-rting Sequence (see S^cti.n 2.1.2) relay H is \ctivvt-.d during th- period chr.t th. ten second timer J is running. Thus, for . p^ri.d cf ten seconds initicl clscjr relay IIo. 3 (in the initiating unit) is ..ctivatcd by .-. circuit through c-.nt«-.ct E,. This chc.ngcs the pottntial jn the screens of certain g;.tcs in the nastor pro- gr.-uaner fron +150 volts to ziro wits (this is called tho master program- mer clear - iPC). This ch-ngi in potentis.1 prevents the corresponding getcs from conducting and, thu- , during this ten sec nd period no prtgran pulses are transmitted from the raster prc-grammer. For ft ne*e complete description of this situ .ticn see Section 10.3.2.
Another o-ntf.ct n initial cle-r relay Ho. 3 opens allowing a 125 mf. c-ndencer to charge up during th3 ten second in-ervel. At the e.id :f the ten second interval relt-.y S is picked up by the c>.nU.ct Jy Contact K4 opens dropping reloys a and iJ &nd r.llowiag the ten Beecnd tintr J t. reset. As H Irois initial dear relay nuaber three drops
II-9
changing the bias on the screens of the gates in the master programmer (IPC) hack to +150 volts, mother contact on this relay closes allowing the 125 laf. condenser to discharge through the coil of initial clear relay Vo. 4. This relay is activated for a period of about one second and changes the potential on the initial clear line froa -345 volts to -290 volts. T::is produces the initial clear gate (ICG). This initial cl^ar lin« goes around to th6 various units by way of the d-e wiring channel.
Tht initial clear circuits work automatically at the end of a starting sequence or with a d-c on s<?qu3nca» The initial clear sequence also tuic&G pls.C6 when the initial clej" push button is operated (on front ponal of the initiating unit, st& PZ-9-302).
There follows u lint of thin_c which t_kc place in the various units during th* process of initially clt»-ring.
(1) Initiating Unit (sfcs PX-9-307).
The initial cl^^r gate (ICG) thres gates which pass central prograa pulses (CFF) which r^ss-t the reader and printer start flip-flops (65, 6S, Jid 68, 69 on PI-.S-104) *nd the re^d.r interlocl:, reader finish, and the r--dsr synchronizing flip-flops (67. 68 ana 70, 71 on PiI-9-103 and 63, 64 on PX-9-106). (S,„ tactions 8.2 <-nd 9.1.2.)
(2) Cycling Unit (?;i-9_307).
The initial clear j*to is not used in the cycling unit.
(3) accumulator (PX-5-304).
Th* ICG 0ates Ctntr^-l projrui -ulses ./hich cause th«» decades =-nd the PL. count.r to cle.o- b«ck to tbe-ir first stages (or possibly sou* dost.de mc.y el&ar to fivs for round-ofi* purposes) and the r^pe-ter ring
11-10
(associated with the truisc-ivers) to clear back to stfegc one. (See Sections 4.2.3 and 4.1.2.)
(4) High Speed Multiplier (P2-i-308).
Here ths ICG gates central program pulses which step the progress ring to stag< one (s*e Section 5.3) snd which reset the 1 and r rcseivers (which control the product .wcumulktors in the process of r=rceiviag tn* psurtiai products).
(5) Divider aid Squtjrc Rooter (F^10-304).
The ICG gates central program pulses producing CI and CI* pulses which perform the clearing actions as described in Section 6.2.9. .xtually these pulses clear the program, ring, the quotient place, ring, and tho numerator binary ring, and rosct numerous flip-flops*
(6) Function Table (-'2-7-304).
The ICG gates central program pulses which cl.ar tho argument rings, the program ring and resets certain flip-flops (see Section 7.4.4).
(7) Constant Transmitter (PX-11-307).
The ICG is usad only in the reader control circuits which are located in the initiating unit, see (1) abovs.
(8) Printer (P*-12-307).
The ICG is used only in thb I3iu punch control circuits which ari located in the initiating unit, sea (1) above.
(9) Kast-»r Programmer (FX-8-304)
The ICG 0.rtes central program pulc^s which cUar the d,cade rings and th» st^p^r rincs (see JoCtions 10.2.1 and 10.3.1).
If any progra... puis*.. get started in the trays and jumpers which extend around the ...achin. (thiy might get stated whin tn*. d-c
11-11.
power cones since certain flip-flops nay come on in th* set or abnormal position) they will run out any sequence which sn operator has plugged in. Ker!7cv«r, if any of these sequences pass through the master program- mer the pulses will not pas3 here during the initial clear period (because, ths master programmer clear (*PC) blocks the program output Sites, see Section 10.3.2. Th* period during which th& initial clear is on is ample ( including a saf ety factor) for any manually plugged sequences to run out (assuming that no one has plug0ed in any compl*to cycles of programs which do not pass through the master programmer). Then, a'ter the. initial cle«j- sequ-noe is completed C^nd the ready pilot goas on) th? machine is re<-.i.y to start any sequence of computations vrhich nay bi programmed,
2.2 ETITIATIHG FULSE PROGR*. CCiTTR0L
The initiating pulse plug-in unit is activated by a push button and produces a program puis© which is synchronized with the El'lrtC. This pulse appefjrs r.t c. terminal I on the front panel (FX-9-302) *Jid c-ji b; jj-jriad around the program, trunic syst-n to any unit of the ZHInC.
This unit is pictured in the upper right hand corner of PX-9-307. Closing the initiating pulse push button causes the special pulse standardirer (tubes 61 rnd 62) to set the flip-flop (64 and 65). This op^ns the gate 66 which passes a central progr*-. pulse (coning free the cycling trunk) setting flip-flop 67 and 58. This flip-flop opens gate 69 passing a CFP which rtsvts both flip-flops and goes through the transmitter to the output terminal IQ (s*e PX-9-302) on the front panel.
IX -IS
The two flip-flops operating as described above always provide a standard output prolan puis*. Gate 66 nay open in. such a way that only part of a CFP is pos.*d. If it fails to operate flip-flop 67 and 68 no hero is done since flip-flop 6* *n4 65 is not reset and the next CPP is passt-d full strength by g.te 66. Then the flip-flop 67 and 68 has one full addition tine in which to set up so ^ate 69 is open end passes i: standej-d pro^xi pulse. This pulsc then resets the flip-flops and is transmitted.
There is no cross secticn di&gran of this circuit. Clerjly, cine* ther; is no parallelise, af circuits in this unit, a crosi section nust be sx detailed as the actual ^irin^ dic.~rea of the circuit. The nunber Pi-9-105 in tb_ corner of the drawing of the plug-in unit refers to the wiring diagr«c
2.3 OTHSl FEUTUBE&
2.3.1 S«l*stivs Clear Controls
There axe six transceivers loceted in the initiating unit with program input and output terminals on the front pp.nel. Th= output of the cathode' followers of the respective transceivers Is connected to s line of th* cycling trunh *.nd provi-'is the selective cle^jr gate (SCG). This Sate is u3ed to oleur ^ny of -sh* tv^nty .-.ccu^ul-tors depending upon the settings jf their selective cieer s-itch-s (s*e Section 4.2.3).
Thus, whenever a pro^r-j-. puis* inters one of the terminals C tho selective cleu g<ite is prrvid*d fr>r t. period of ~nc Edition tine End c pro^r.-.a pulse is tr.-ns itted cat ;€ the terr.in^.1 Co at the *nd of the r.dditi.:n tine. These tr -nsciiv=-rs :-j-e re:*t by a CFP :.ft-r one .\ddi-
II-. 13
tioa tine. A nore detailed Mock ditj^n representation of a transceiver
£.pp=trs on FX-5-304.
2.3.2 Reader and Printer Pro»jan Control
Control circuits for tie XBK reader and the IBii mm punch are located on plu^-in unite (see the four plug-in units beloc the initiating pulse plug-in unit on PX-9-307) located in the initiating unit.
These circuits ire described in detail in ths discussion of the
constant transmitter (Chapter Till) and of the printer (Chapter IZ). 2.4 TSoTIIfO FILrJURZS
On the front pon?l of the initiating unit thsre appears e. hue oscilloscope, an a-c voltuet^r, and k d-c voltnst-r. 7h*»= cje used to chrch the anount of hua on th» a-c pa.rer lin*s supplying the £JT«Ct the voltages en th- thrfes ph;.s& lines supply the a-c power, end the d-c voltages put out by the pwrf supply. Two switches ^at-ble the operator to ehsCk sVtrry d-c vc;ltcu~ used in tlie r...chine. k t»-ble Jt proper Tr.lu-:s and tolferejxcos appears on this ptuiol.
Per :-. cocplatc discussion of testing procedures, tt cetera, the reader is referred to th* u;.intenetncs nanual (p-rt III cf this report).
in - 1
III. CICLBCUMT
The cycling unit produces the pulses which are used to represent digits and to control the operation of units of the ENIAC. Also the carry- clear gate (CCG) is produced in the cycling unit; The pulses produced in the cycling unit control the timing of the operations and enables the TBiiou* units to operate in synchronism.
The following table gives a list of the pulses or gates produced in the cycling unit. Also appearing in the table is the principle purpose of each pulse or gate.
TASX£ 3-1
|
Pulse or gate |
Abbreviation |
Purpose J |
|
.Central Program pulse |
CPP |
A program pulse used to control the activity of the various units of the ETIAC. |
|
(Tens pulses !(off beat) |
10P |
Used to cycle the decades of the accumu- lator during the process of transmission of the nuaber (or its complement) regis- tered in the accumulator. |
|
One pulse ! jTwo pulses Two-primed pulses Four pulses |
IP 1 • 2P 2'P UP J |
* coded system in the multiplier, function tables, and the constcnt transmitter makes use of combinations of these pulses to represent the digits zero to nine. |
|
!Nine Pulses 1 |
9P |
Sone of these pulses are used to rep- resent the digits zero to nine. |
|
One-primed pulse |
l'P |
In the process of taking the complement this pulse is used to obtain the cample- nent with respect to 10° instead of ld»-*. |
|
Reset pulse |
RP |
This pulse is used to reset flip-flops in the accumulator decade units and to pro- vide a carry-over pulse In the process of addition. |
|
Carry-clear gate |
CCG |
This gate controls the carry over process when adding in an accumulator and produces the clearing action when so desired. 1 |
in - 2
The pulses and gates listed in the table above are produced in the cycling unit once each addition tine* PX-9-306 shows the temporal order of these pulses and gates. These pulses and gates along with the selective clear g?te from the initiating unit (see 2.3.1.) arc distributed around to each unit of the EEIAC by the cycling trunk.
An addition time is normally 200 micro-seconds long. Each addition time is divided into twenty parts called pulse times, each ten micro-seconds long. All of the pulses except the 10P are produced at the beginning of a pulse tiac end all have a duration of about two micro-seconds. The tens pulses (10P) pass through a 2.5 micro-second delay line and thus arrive at the beginning of the second quarter of a pulse time. The tens pulses, 10P, are used to cycle decades in the accumulators (see A. 3.) during the process of transmitting the contents of the accumulator. These off-beat pulses arc produced 2.5 micro- seconds late for timing reasons which will be explained in the chapter on the accumulator (see 4.3.1.).
3.0. E.TR0DUCTI0N
The block di?gram of the cycling unit along with that of the initiating unit appears on PX-9-307. In the upper left corner is the oscillator plug-in unit. To the right of this are the relays which determine the mode of operation: continuous, one addition time, or one pulse time. Below the oscillator plug-in unit are two more plug-in units containing pulse standardizes and delay lines, hear the middle is the twenty stage ring which counts out the pulse times of an addition time. B^ow the ring are pulse gates, than the amplifiers, and finally the transmitter plug-in units. The outputs of the transmitter plug-in
Ill- 3
units go to the cycling unit trunk which carries the rarious pulses and gates around to each unit of the ENIAC.
fX. THE OSCILLATOR AND PULS&
3.1.1. The OsciHator
The crystal oscillator always oscillates at a frequency of 100 kilo- cycles. Whether or not the output of the oscillator is used depends upon the setting of the external oscillator switch and the continuous and one addition time relays. The socket and the external oscillator switch makes it possible to operate the ENIAC with an external oscillator, and, more important, to operate the ENIAC at different frequencies for purposes of checking (for example, tc check safety factors)*
Note: If the ENIAC is operated at a frequency exceeding 100 kilo- cycles the safety, factors may be lost and reliablo operation cannot be expected.
The continuous and one addition time relays cause the oscillator ( external or internal) to be connected through the pulse standardizer K-L 26 to the gates L27 and L28 for continuous and one addition time but not for ane pulse time operation. Of the three modes of operation the first (continuous) is the normal mode and the following description will be in terms of this mode. The =ther two modes (one addition time and one pulse time) are for purposes of checking and will be described in section 3.3.
When the continuous relay is activated the cathode circuit of tube 70 is opened, thus turning tube (70) off and, therefore* opening gate L28. That is, since tube 70 is not conducting the plate potential is relatively highj and, therefore, one of the control grids of the gate L28 is sufficiently high
in ~ 4
that any positive signal on the other grid will cause it to conduct. Hence, the output of the oscillator goes through the contacts on the continuous relay to the pulse standardizer K-L 26 and through the gate L 28 to the en-btat plug-in unit.
The pulse forming circuit, composed of a special pulse standardizer (tubes 68, and 69, see section 1.2.7.) and tube 70, serves no other purpose than that described above in continuous operation. Its role in one addition time and one pulse time operation will be described in 3«3« 3.1.3. The on-beat plug-in unit
Tubes 61, 62, 63 of the on-beat unit constitute a pulse standardizer. This circuit differs from the usual pulse standardizer in that it has a one micro-second delay line on the plate supply of tube 62. By reflection this delay line helps to produce a square pulse with a length of two micro-seconds.
The output of tube 63 goes to tubes 68 and 67 and thence to a socket located underneath the front panel. Thus, pulses (which are in phase with the nine pulses 9P) arrive at this terminal in the following ways:
a) for continuous operation one pulse each pulse time,
b) for one addition time operation twenty pulses (one each pulse time) each time the push button is operated, and
c) for one pulse time operation one pulse each time the push button is operated.
The output of tube 63 also goes to tubes 65, 64, and 66 and on to the pulse gates controlled by the ring. These pulses are gated by the ring to pro- duce all pulses sent out by the cycling unit except the tens pulses (10P).
The third output of tube 63 goes to the off-beat pulse former plug-in unit and enters a £.5 micro-second delay line.
in -5
3.1.4. Th£ off-beat plug-in unit
From a center tap on the 2.5 second delay line pulses go through a pulse standardizer (tubes 67, 68, 69, and ?0) and thence to step the ring. This pulse standardizer is similar to the usual pulse standardizer (used in accumulators) except that it has two driving tubes (67 and 68) operating in parallel.
The end output of the delay line goes through another pulse standard- izer to the tens pulses gate L30. This pulse standardizer also has a one microi* second delay line to obtain square pulses of 2 nicro-second length.
The pulses which step the ring arrive 1.25 micro-seconds after those that go to the pulse gates which are opened and closed by the stages of the ring. This means that the ring has 8.75 micro-seconds in which to step from one stage to the next, and for reliable operation the ring is designed to step to the next position in appreciably less time than this.
3.2. THE RING AND ITS ASSOCIATED G^TES kND FLIP-FLOPS
3.2.1. The tens pulses (10P)
YJhen the ring is on stage 0 gate K27 is open. Thus the first pulse of the addition tine passes K27 *nd sets the flip-flop L29. This flip-flop most open gate L30 inside of 2.5 micro-seconds in order to pass the first of the tens pulses arriving from tube 61 in the off-beat pulse former. Thus, this is not a standard flip-flop; that is, the triggering tubes are omitted in order to improve- the time constant. Also, the output time constant is less than for a str.ndard flip-flop.
The output of gate K27 also goes to trigger the scope which is
hi ~4
located on the cycling unit. This gives one addition time sweeps on the «eopo»
The flip-flop L29 remains set until the ring reaches stage ten. At that tine the output of gate A30 resets the flip-flop. Note that in order to not pass more than ten pulses the flip-flop must reset in less than 2.5 micro-seconds .
The output of L30 goes to a two stage amplifier (LU. to U+4) and thence to two transmitter plug-in units, k transmitter consists of t'|> stages with five tubes operating in parallel in each stage. 3.2.2. The 1^ 2^ 2J_,_ 4. and £ Pulses. The ons jft&ae (IP)
When the ring is at stage one gate K30 is opened to pass a one pulse. The pulse goes through an amplifier system (K41, K42, K43, K44, K46, and K47) to a transmitter plug-in unit. The two pulses (2P).
Stages two and three of the ring open gates J30 and H30 to pass pulses to form the two pulses, «fter being preamplified by J41, J42, H41, and HU2 they are combined and further amplified by J43, J44, J46, and J47, and then fed to a transmitter plug-in unit. The two-primed pulses (2'P)
Stages four and five open gates G30 and F30 which pass pulses to nake up the two-primed pulses, ns with the two pulses these are amplified and taken to a transmitter plug-in unit. The four pulses (UP).
Stages six, seven, eight, and nine open gates £30, D30, C30, and B30 to p^ss pulses which make up the four pulses. These are amplified and taken to a transmitter plug-in unit.
»';.'•'«.
hi - 7
The nine pulses (9P)
The one, two, two-primed, and four pulses are taken to buffers KU5, J^5, GU5, and ^5 and then combined to make up the nine pulses. Then they pass through a two stage (six tubes in parallel) amplifier- (* 2fc an* 2* to F2Z* and 25) and then to four transmitter plug-in units, 3.2.3. Jh£ one-prined pulse (l'P).
Stage ten opens two gates -A30 and a27. Gate -A30 passes a poise which resets the teas pulse flip-flop. Gate ~27 passes the one-priraed pulse through amplifiers «26, B26, A23 to E23 and F23 to K23 and then to three trans- mitter plug-in units. 3.2.4. The carry clear gate (COG)
Stage eleven of the ring opens gate B27. This gate passes a pulse which sets the flip-flop E27. The negative output of the flip-flop goes through amplifier tubes D26 and D27 to a transmitter plug-in unit. '.Jhen this flip-flop is set this output takes a positive swing and the transmitter gives a positive gate on its output. Note that this -iroplifier system is direct coupled all the way through. The carry-clear flip-flop is reset when the ring r reaches stage eighteen. The length of this carry-clear gate (70 micro-seconds) is about 1 3/4 times that needed for carry over in a twenty decade accumulator, th?.t is, when the carry jver takes place there nay be a string of carry overs frraB the first decade down to the twentieth. This gives a seven to four safety factor which is somewhat less than the two. to one which is attained in most parts of the EJJIAC.
in - 7
''ho nine pulses (9P)
The one, two, two-primed, and four pulses are taken to buffers SA5, J^5, G45, and ^5 and then combined to make up the nine pulses. Then they pass through a two stage (six tubes in parallel) araplifier (*. 2£ and 25 to F24 and 25) and then to four transmitter plug-in units. 3.2.3. The one-primed pulse (l'P).
Stage ten opens two gates -A30 and i»27. Gate .±30 passes a pulse which resets the tens pulse flip-flop. Gate «.27 passes the one-primed pulse through amplifiers »26, B26, A23 to E23 and F23 to K23 and then to three trans- mitter plug-in units. 3.2.^. The carry clear gate (CCG)
Stage eleven of the ring opens gate B27. This gate passes a pulse which sets the flip-flop E27. The negative output of the flip-flop goes through amplifier tubes D26 and D27 to a transmitter plug-in unit. *&en this flip-flop is set this output takes a positive swing and- the transmitter gives a positive gate on its output. Note that this amplifier system is direct coupled all the way through. The carry-clear flip-flop is reset when the- ring r reaches stage eighteen. The length of this carry-clear gate (70 micro-seconds) is about 1 3/4 times that needed fcr carry over in a twenty decade accumulator, that is, when the carry over takes place there may be a string of carry overs from the first decade down to the twentieth. This gives a sev~n to four safety factor which is somewhat less than the two to one which is attained in most parts of the ENIAC.
in - e
3.2.5. The reset pulse (RP)
Stages 12, H, 15 , and 16 of the ring do not operate any gate*, Stage 13 opens gate C27 and passes a reset pulse. Stage 19 open* gate JZf which also passes a reset pulse. Thus, in each addition time there are two reset pulses, one when the ring ±s at stage 13 and another when it is at stage 19. The output of the gates C27 and J27 goes to an amplifier system B26, G26, G to J 24 and 25. The output of this amplifier goes to three trans- mitter plug-in units.
3.2.6. The central program pulse (CPP)
Stage 17 opens gate G27 which passes the central program pulse. Since this pulse is used more places by far than any other pulse in the ENIaC it goes through the largest amplifier system. This pulse goes through tubes F27, F26 and E26, then to a two stage (ten tubes in parallel) amplifier (A22 to K22 and A21 to K21) . The output now goes to nine transmitter plug-in units which constitutes a two stage amplifier with forty-five tubes in parallel in each stage.
3.3. ONE PULSE AND ONE ADDITION TIME OPERATION
These two modes of operation are provided for purposes of checking the operation of the ENIAC and to check the set-up of the problem. If the answer to a check problem is not correct then it becomes a matter of isolating the fault. This generally can be done by operation in the one addition time Bode. Then, operation in the one pulse time m-xie will generally further help to diagnose the fault. For further discussion on these points see part I of this report.
in - 9
3.3.1. One addition tine operation
In this case the transfer contact on the continuous relay holds the cathode of tube 70 (in the oscillator unit) at -40 volts. This tube is noraally on and vdll go off only upon receiving a negative signal front tube 69 which gets its stinulus fron the push button.
The length of this pulse sent to gate L28 oust be long enough to be sure to let a pulse fron the oscillator through (at least ten microseconds). This first pulse which passes gate L2S steps the ring fron. stage zero to stage one. Since .sue of the control grids of gate L27 is connected to the negative static output of stage zero, gate L27 is opened as long as the ring is not at stage zero. Thus, the pulses from the oscillator (via K-L 26) continue to step the ring until it reaches stage zero again. Hence, each tine the one pulse or one addition tine switch is pushed the ring cycles through all twenty . stages and the cycling unit gives out the various combinations of pulses which represent one addition tine. Note that the pulse sent to gate 128 by 70 nust not last as nuch as one addition tine or else operating the one addition tine push button nay cause the ring to cycle twice. 3.3.2. One pulse tine operation.
In this case neither the continuous relay n.^r the one aadition tiae relay are activated. This ncans that the oscillator output is not connected at all. The output of the first triode of 70 goes both to the second triode and to gate L28. The output of the second triode goes through contacts on the one addition tine relay ?nd the continuous relay to the pulse standardizer K-L26 ind through the gate L28. Thus, each tine the push button is operated one pulse is fed into the on beat plug-in unit.
Ill - 10
The wide pulse from tube 70 which is applied to gate L28 is delayed (because of the tine constants of the path through the relay and the pulse standardize!*) and differentiated (narrowed) by the pulse standardizer circuit* This p.ssurcs its being gated at L28 by the wide pulse from tube 70 on the other control grid.
IV. ACCUUUUTOR.
An accumulator is a unit of the ENIAC which is capable of perfom. ing the foUpvring operational
1) Storing a ten digit number along with the proper indication of its sign,
2) Receiving numbers (positive or negative) from other units of the ENIAC and adding them to numbers already stored, properly indicating the sign |f the sum.
3) Rounding off its contents to a previously determined number of places.
4) Transmitting the number held, Or its complement with respect to 10 , without losing its contents (this makes it possible to add and/or subtract from the contents of one accumulator those of another).
5) Clear its contents to zero (except for a possible round off five, see 4.2.3.).
6) Information stored in certain accumulators may be transmitted statically to certain other units (see Section 1.1.4.)
The registering of ten digit numbers is accomplished by the use of decade ring counters (See 1.2.2.) and a Hi (plus-minus) counter. The circuits which carry the various groups of pulses representing numbers and signs (in- cluding the decade plug-in units and the FM-Clear plug-in unit except for the clear tubes) will be called the numerical circuits. The accumulator contains common programming circuits which in each operation of the accumulator determine which of the above listed operations the unit performs. The accumu- lator contains a number of program control circuits (eight repeat program control circuits and four non-repeat program control circuits) which can be used at various times to cause the common programming circuits to make the
17-2
accumulator perform one of the above operations.
Thus, usually each program control circuit will be used at most once in each sequence of computations whereas portions of the cannon program- ming circuits are used each time the accumulator performs an operation. So two program controls are used simultaneously. Actually by making use of the master programmer it is possible to use one program control circuit several times in a given sequence of computations. The operation performed by the numerical circuits (controlled by the cannon programming circuits) is deter- mined by the various switch settings of the particular program control used.
When activated by an incoming program pulse (arriving via jumper connections from program trays to the accumulator front panel) the program control circuit provides certain gates to the common programming circuits which in turn supply certain g;;tes or pulses to the numerical circuits and thus cause the accumulator to perform a certain operation. At the end of the operation (which may last as many as nine addition times if a repeat program control circuit is used) the program control circuit gives out a program pulse which may be taken to other units of the ENIAC causing them to perform the next step in the sequence of computations. 4.0. INTRODUCTION.
This description of an accumulator will be given in terms of the block diagram PX-5-304 and the cross-section diagram PX-5-U5. In the upper center and upper right of the block diagram there are eleven rectangles rep- resenting the ten decade plug-in units and the FM-clear unit (on the left). Just to the left of the PU-clear unit are seen the five decks of the signifi- cant figure switch. In the lower left hand corner are seen one receiver plug-in unit *nd two tr;nsceiver plug-in units. As indicated on the drawing there is one other receiver plug-in unit and six other transceivers making a total of four receivers located on two plug-in units and eight transceivers
IV - 3 each located on a separate plug-in unit. Just above the code block and below the decade units are the a, fi, y, 5, and e input gates of which only a and e are shown in detail.
As indicated above, the circuits of an accumulator are divided into three groups for purposes of explanation. First, there are the program con- trol circuits which comprise the circuits of the receiver and transceiver plug-in units, their associated switching circuits, and the repeater plug- in unit. Second, the common programming circuits connect by means of inter- connection plugs (see, for example, the terminals marked ST 6, 7, and 8 on the left edge of PX-5-3Q4) to the program control circuits. Third and last, there are the numerical circuits which extend from the input plugs SV , ..., SV through the decades and PU unit to the output plugs SW and SW2 (at the top of the block diagram). The coninon programing circuits directly control the numerical circuits by opc-ning certain gates and in 6ome cases introducing certain pulses into the numerical circuits. The following table summarizes the gates and pulses produced by the program control circuits and by the concon programming circuits.
IV -4
TABLE 4-1.
Brogriu Control Circuits
Sv.dtoh aetilr^s
Opcr^-ioii . OIcj-j * R po.-t Switch : 5»-itr:h : S'«it.-h
SU 1
— SU 2
3U 10
Carry sate to tubes 19 and 20 in the decades and a input j E^tes opened. I
None
Carry gate as above I and 3 input gates j opened.
Gates .-E49 and E50 j _op_jncd.
-J
V_ pulse added i in first decade j
SU 6
Gatos H47 cJid J49 opened.
Tens pulses to cycle decades and j Nines pulses for I transmission ove^ ) add output STi\
Gates G47, G49, j Tens pulses to ~ "
H49, and M41 opened*. ! cycle decades,
i Nine pulses for
i transmission ovef
1 add output and
! subtract output,
j and One-primed
j pulse for trans-
| mission over SW2
AS
— I SU 7
• 0
SU 3
Gates F47, F49, and M42 opened.
WT
SU 9
Same as for *' above
Opens U44 passing CCG to clear tubes in the PM-Clear unit.
I Tens pulses to
1 cycle decades,
j Nines pulses for
! transmission over
! subtract output,
and One-primed
1 pulse for trans-'
J mission over SW,-:
J 1 .
I Sane as for A I above
IV-5
J».l. THE PROGRAM CONTROL CIRCUITS
Ul.I. General description of a non-repeat program control circuit
Suppose that a program pulse arrives over the input terminal li (lower left corner of PX-5-30/J. This positive pulse will cause one half of 66 (tube 66 is a 6SN7, a double t*iode tube) to become conducting. The drop in plate voltage will send a negative pulse inta the flip-flop1 causing it to be set. The indicated polarity of the output will then be reversed and half of 62 will go off (become non-conducting), causing the cathode follower1 63 to go on. The output of 63 comes from the cathodef therefore, when the tube becomes conducting the cathode potential rises with respect to that of the plate giving a positive gate voltage on the output. This output goes to dock 3 of the operation switch. If the operation switch is sot ?.t a, 3, y, o, or e this positive gate voltage appears on the interconnection terminals labeled SU 1 to 5. If the switch is set ■>Jb A, A3, or S then the gate appears on SU 6, 7, or 8. The fast output (cr.thode follower) is used there since these circuits must be set up before the 10 pulses arrive. The other output of the receiver flip-flop (which is positive after being set) opens the gate 61 (that is, allows a pulse on the first grid to cause the tube to conduct) and turns the buff r 62 on. This gives a negative voltage swing on the output which goes through the clear- correct switch and deck 2 of the operation switch. If tte switch is set at a to e, this signal appears on terminal SU 10 and will c^use the correction to take place. If set at 0, A, a£, or S the signal turns the inverter F50 off and the buffer (the other half of F50) on, giving a negative gate ^t SU 0 and will camse the accumulator to cletr. *fter the gate 61 in the receiver is opened, the CPP (Central Program Pulse) arriving at the end of the addition tine resets the flip-flop. Tke tiie constants are such that
T) For~a detailed discussion of flip-flops, gate tubes, buffers, and inverters see Section 1.2.
IV - 6
gate 61 does not open in time to cause any conflict with the CPP which
activates the receiver.
4.1.2. General description of a repeat program control circuit
Now, suppose a program pulse arrives at a transceiver, say at input terminal 5i. As in the receiver this pulse sets the flip-flop and within 15 us. gives the positive gate through deck 3 of the operation switch tc the interconnection terminals SU 1 to 5 or SU 6, 7, or 8. The other output (which is now positive) of the flip-flop turns the buffer tubes 61 on and opens the gate tube 62. If the clear switch is setting on clear, the negative gate output of tubes 61 goes through two decks of the operation switch and appears at SU 9 and at SU 10. The two tubes F50 are in the line from the receivers to raise the circuit to the d-c voltage level of outputs of the transceivers. The cross section of the receiver and transceiver (see PX-5-115) shows that the plate supply of the buffer 62 in the receiver is -345 whereas the plate supply of the buffer 61 in the transceiver is -235 volts. The negative gate from the right hand buffer 61 in the transceiver will turn the inverter J50 off giving a positive swing to one of the grids of the gate tube H50. The central program pulses (CPP) arriving at tube H50 will now be passed on into the repeater rinr. (The CPP that stimulated the program con- trol will net be passed). They go through the pulse standardizer (tubes 61, 62, and 63) and step the ring. If the repeat switch is set at 3 (as illus- trated), then at the third addition time the ring will have stepped to stage three giving a positive gate through the repeat switch to the gate tube 62 in the transceiver. Note, that one repeater ring is used
1) This follows tho practice that circuits are designed to operate in not more thui half of the time which would suffice, for example, the 10 pulse gates (F-4, 47, connected to SU 6, 7, and 8) must be open inside of 32 ps. (After CPP sots receiver or transceiver) in order to pass the first ten pulse. Actually, the time constant for those circuits depend upon the set- ting of the program switches. The maximum time constant occurs on a circuit when two accumulators are interconnected to form c twenty digit accumulator and all program switches are set to activate that circuit.
IV - 7
by all the repeat program controls. This causes the inverter 65 to go off opening the gate 68 and turning the buffers 63 on. The output from cne of the buffers 63 goes through the clear switch and the operation switch giving a negative gr-te at «! 9. Trie output of the other buffer 63 turns the tube J50 off opening the -ato i$G (this process of opening gate K50 takes about 100 vz*) Ems :P? ~t th_ cr.d of the third addition time passes this gate and turns the ir.vcrt.rr K49 c-ff (it over-rides the stepping pulse frost H50) clearing the repeater *-in,T Sack to stage one, Tha gate 68 being open, the central program :;ulse arrivee at the end of tho third addition time, resets the flip-flop, end feeds through the transmitter (tubes 70, 71, and 72j giving a pi-ogrom output pulse which can be used to operate some ether unit during the fourth addition time. 4.2. THE CCfcOON FFOOLA-iilNG CIRCUITS 4.2.1. The receive tj circuits.
The receivTr.g circuits cause the accumulator to add to its present contents any ten digit signed number arriving through the input plugs SV\ to SV . Tiis addition is accomplished by opening the proper set of receiving gates (L to A 41, L to h. 42, ,.., or L to «. 45 )> and oy providing for the carry-over between the various decades.
Supp se that -*n activated program control has its operation switch set on a. This applies a positive gate to SU 1. The inter connector cable carries this to ST 1. then it will cause tube C43 to become conducting and turn off the inverter J46. The positive gate from J46 opens the gate tubes LU to A 41 and any digit or FM pulses arriving at the plug SVX will bo transmitted into the corresponding decade or Ri unit. «.iso, the positive gate from STjl will open th* gate tube E47 allowing the carry-clear gate (CCG) to be passed to the inverters A to D 49. The output from these in- verters thon opens the carry gates 19 and 20 in each decade. This carry- over will be expl-'in-^d in detail when the numerical circuits arc taken up. (see Sec. 4.3.1.).
IV - 8 If the clear switch is set on C and the operation switch on a, then a negative gate will be applied to inverter G50 turning it off and open- ing the gates E'+9 .Mid 7X0. This passes the 1' pulse through the ictercoraector terminal? i£L 14 ^n<* L? i2:to the first decade of the accumulator, Th;s pro- vides for *).e eorreatioe of negative number* where some of the last digits have been lest by Uie use of deleter* (aee Section 11.2.) 4.2.2. The add ?Jid subtract transmission circuits-.
Suppose the operation switch of an activated program control is set at AS. Then a positive gate will appear at SU 7 and be transferred b7 the inter connect or jumper to ST 7. Then it will open the gate tubes G47» G49, H49, and M41. G47 will pass the cytling pulses (10 P) to the inverter H48 and the cathode follower L46. The output of L46 operates the buffers B, D, F. H, and K 46 resulting in the decades* being cycled through all ten stages back to where they started. G49 will pess the 9 pulses to the inverter E 48 ^nd the cathode follower D48. From there these pulses go to the gate tubes 22 in the decades and the g^te tube 16 in the PM unit. Similarly, H49 will pass 9 pulses through C48 and F4S- to the- gates 21 and 15. M41 passes a 1' pulse through the transmitter (23, 24 and 25 in the PM unit) to the inter- connection terminals SU, 17. From there it goes to the significant figure switch and into one of the output terminals of the subtract output SW2.
If the operation switch is set at A then the cycling pulses (10P) are provided by gate H47 and the 9 pulses (9P) are supplied to the add gates 21 of the decades and 15 of the PM unit by the gate J49. If the switch is set at S then the cycling pulses are provided by F47 and 9 pulses are sent to the subtract gites 22 of the decades and 16 of the PM unit by gate F49j also, U42 provides the correction pulse (l'P). If the clear switch of the activated program control is set at C then at the end of the operation (one addition time in the case of receivers and one to nine addition times in the case of transceivers depending upon the setting of the repeat switch) a negative
IV - 9 gate voltage will appear at SU 9 and from STj 9 it will turn off the in- verter J50 opening the gate M45. This passes a carry-clear gate (CCG) to the clear tubes fl to 10 in the PM-Clear unit). Z».2.3. Gejoral *.&r-.inj.ip-i of the clear circuits
For pu:pcd«;s of rounding off nunbers the decades of an aconulator are provid-d sdtfc ciear-to-five circuits. To the left of the PM unit is seen the significant figure switch. The sotting of this switch determines which decade clears, to 5^ All other decades dear to zero. For example, to round off to three significant rlgures the seventh decade is cleared to five before the number to be rounded off is put in the accumulator.
Inspection of a decade plug-in unit on the crose-section PX-5-115 shows that clearing any stage in the ring is accomplished by a direct con- nection to the clear tubes (1 to 10 in the PS! unit) labeled "clear T", and a return circuit labeled "clear R" which returns to a resistance. The block diagram shows that all stages except zero and five connect directly to the clear tubes and the resistance, whereas, stages zero and five connect to four decks of the significant figures switch. The significant figures switch effectively reverses the connections to the zero-five leads in one decade causing the decade to clear to five instead of to zero.
With the significant figures switch setting as illustrated, the ninth decade will clejr to five, giving numbers with one significant figure. a clear signal coming from the clear tubes in the JV. unit will go directly to the upper connections to stages 1, 2, 3, U, 6, 7, 8, and 9 in all decades, through deck one of the significant figures switch, it will go to the upper connections to the fifth stages in all decades except the ninth (corresponding to one significant figure) and in the- ninth through deck 2* it will go to the upper connection of the zero stage. The return circuits come hack in a similar manner through decks 2 and 1A.
iv -:o
The clear signal arises by a carry-clear gate being passed by tube 1IAJ+ to the inserter Mi»3 and thence to tube 1 in the P1I unit. If the accumulator is being used with the nultiplicr or divider the clear gate may b introduced directly into the PJI unit as illustrated. The gi.te W*U will be opened to pass a carry-clear gate in the following cases*
a) If the ENIAC is initially cleared the initial clear gate (ICG) arrives through the buffer M45.
b) If the accumulator is set to selective clear and the selective clear gate (SC3) is provided at the initiating unit (see 2.3.1.} then the inverter J5Q is turned off by the signal from the buffer A/»8.
c) Or, if the program control switch of an activated program circuit is sot to 0, A, AS, or S and the clear switch to C then at the end of the operation a negative gate appears at ST 9 wbich turns off the in- verter J50 and opens the gate UkU.
The ICG also clears the repeater ring back to stage one by gating a CPP at K50. U . 2 . U . A description of the interconnection features
The outputs of the program control circuits appear at terminals SO located on the front panels. Just above these are the terminals ST. It is expected that the usual plan will be to operate as a ten digit accumulator. In this case a jumper is plugged from the terminals SUX to ST1 (PX-5-121) and a l*ad box is placed in ST2. T#is effectively connects together the interccnnector terminals located next to each other on the block diagram PX-5-304. In case of twenty digit operation all the program controls must operate in parallel; this means that the load resistors for these circuits cannot be built in since what is correct for separate operation would not be correct when they are operating in parallel. Thus, the l*d resistors are on a unit which is plugged into the front canel. Only one such unit is used with each accumulator or with each pair of accumulators when con-
IV - 11
nected to form a twenty-digit accumulator.
If two accumulators are to be interconnected to form a twenty digit accumulator then the terminals Su*2 and ST of the left hand accumu- lator are jumped respectively to SUX and STX of the right hand, SUj. of the left hand is jumped to ST1 of the left hand, and a load box is placed in ST2 of the right hand accumulator. This makes the earry-orer frx» the tenth decide of the right hand accumulator go into the first decade of the left hand and the 1' pulse (correction pulse) go int© the first decade of the right hand accumulator. The "10" output of the significant figure switch of the left hand accumulator goes to the input of the significant figure switch of the right hand accumulator. The "0" output of the right hand significant figure switch goes to the input of the units decade of the left hand accumulator.
A list of connections for ten and twenty digit operation are given in tables k-2 and 4-3. Note that the R£ unit of the right hand accumulator is not used in twenty digit operation. 4.3. NUMERICAL CIRCUITS 4.3.1. General description of a decade plug-in unit.
The pulse standiTdizer (tubas 11, 12, and 13) consists essentially of four triodes (11 being n double triode 6SN7). The output of tube 12 goes both to tube 13 and the gate 14. ^ The output of 13 goes to the decide ring. In the block diagram the L-rge numbers in the stages of the ring represent the positions of the tube while the smoll number just outside the respective stages represents the digit corresponding to that stage. *fter clearing, the ring is setting at zero (for a detailed discussion of the operation of ring counter circuits, see 1.2.2.).
Receiving lumbers. If five pulses arrive on the digit input they will P'-ss throu-h the- pulse st-nd^rdizer and step th; ring up to position five. Palses will -lso go to the g'.te tube 14 but will lrve no effect since the second grid of that tube is negative being connected to the negative output
IV - 12
TABI3 L-2
Vertical interconnecter cable. (PX-5-121) Just one used for either a 10 *r 20 digit accumulator.
SO,
ST,
|
1 |
2_ <\ |
|
|
2 |
2 |
|
|
3 |
3 |
V |
|
U |
U |
|
|
5 |
5 |
|
|
6 |
6' |
> |
|
7 |
7 |
|
|
1 |
||
|
8 |
8 i |
|
|
9 |
9 |
|
|
10 |
10 |
|
|
11 |
11 |
|
|
12? |
12 |
|
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13 |
13 |
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15-4 |
, — U I i — 15 |
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16 |
16 |
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17 |
17 |
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IS |
ie |
These connections enable any program control circuit to cause the cemmon programming circuits to make the accumulator reeeivsJan enamels
These connections enable any program control circuit to c:use the common programming circuits to make the accumul:tor transmit on A, AS, or S. This connection takes cere of the clearing action. This connection provides for the correction pulse.
This connection in th. ST. end takes the carry of the 10th decade into the input of the HI unit.
This connection tJccs the correction pulse transmitted by the transmitter (2>25) in the Pl£-Clear unit to the input of the significant • figure switch.
Terminal 18 is a ground connection in each case. Note that the load box plugs into terminal ST_ :jid has jumpers which connect terminals 14 and 15 rjid 16 nnd 17. This takes the correction pulse into the units decede input (units decide of right hand accumulator in case of twenty- digit operation) snd the 16 to 17 connection takes the "10" output of the significant switch to the units channel of the subtract output.
IT -13
Horizontal interconnect or cable. (PX-5-110),
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1 |
1 |
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2 |
2 |
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3 |
3 |
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4 |
4 |
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5 |
5 |
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6 |
6 |
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7 |
7 |
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S |
8 |
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9 |
9 |
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10 10 |
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11 |
11 |
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12 |
12 |
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13 |
13 |
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U |
H |
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15 |
15 |
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16 |
16 |
17
17
1?
These connections cause any progrcua control t© cause the two accumulators to act in unison when receiving on a to e .
These connections cause the rccuaulators to act in unison when trr.smitting on a, .^S, or S.
This connection c-uses the clear circuits to act in
unison. J. This connection -Hows any program control to provide | the correction pulse at Umin-1 ST2U of either ^ accumulator.
( For upper cable this connection tskea the output of 1 the 10th decade of right hend :-ccunulator to 1st decade I input of the left hand accumulator. "
J This connection in upper cable takes "0" output of j significant figure of right h-nd accumulator into the | units channel of the subtract output of the left h*nd
accumulator. , . «. i
/ This connection tskea "10" output of th. significant 1 figure switch of the left hand accumulator to the in- I put of the significant figur- switch of the right hand 1 accumulator. «.««■
Termnal 18 is a ground connection in all c ses.
^connections 15, 16, «?,«. -^"J W«je in
the lower interconnect cable (betuecn terminals
9} and SJ2).
IV - lh of the ninth stage of the decade ring. Suppose that six more pulses arrive. Four of these will step the ring up to position nine. The fifth will step the ring from nine to zerc and will pass through the gate H setting the decade flip-flop end turning the inverter 15 off producing a positive pulse at gate 19. Since the incoming digits arrive before the cany gate goes on (sec PX-9-301) this pulse does not pnss grte 19. Ths sixth pulse steps the ring from zero to one. The carry gat: comes on later in the addition Hwt opening gates 19 and 20. Since the flip-flop has been set the reset pulse RP (which arrives just after the carry gate comes on) is passed by gate 18 through the inv.rter 15 and through gate 20 to the digit input of the next decade to the left. This is colled the delayed carry-over. Thus, six plus five is eleven.
Suppose that a decade registers nine and a carry-over arrives from the next decade to the right. This carry-over pulse besides stepping the ring from nine to zero also pusses through gate 14. turning off the inverter 15. This gives a positive pulse to g^te 19 and since the carry gate is still on, there is a carry-over to the next decade to the left. This is called the direct carry-over. If all decades register nine, one may have a sequence of nineteen such carry-overs in the case of a twenty-digit accumulator so the c-rry gate has been made sufficiently long to provide for this possibility.
Transmission of numbers. The above description of a decide unit h-s beun in terms of receiving numbers. Now consider an activated program with the program switch set to AS, say. In this c^-sc the cycling pulses are arriving at the digit input, there is no carry over since the carry gates a to E 47 are not open, and the nines pulses (9P) are arriving at the gates 21 and 22 in the decade. As indicated in the diagram, normally (after initially clearing) gate 22 is open. Suppose the decade registers tho digit three. Hhat happens during the twenty pulse times of an addition time is
IV - 15
illustrated in the table k-h. Note, th~t the tens pulst-s arrive 2 1/2 va. after the nines pulses; this gives the decade ring 7 1/2 us. in which to step and also 7 1/2 us. for the flip-flop (16, 17) to be set. If the operation switch is set , at A insterd of AS the only difference is that the 9 pulses do not appear at gate 22 ,nd the 1' P is not pravidfctU In. case the switch is set at S the 1' P is provided ^nd the 9 P appear only at
gate 22. If the clear switch is set to C then at pulse tine 10 the carry- dear rate appears at gtte tube U45 and the decades :rt clcured back to zero. 4.3.2. Generr-1 description of a PM - Clear plug-in unit.
The Pli-Clear unit contains 2 binary counter to register the sign (Pi!) of numbers. Since the binary counter is muoh simpler then the decade counter the- pulse standardizer is also simpler. It contains three tubes in two envelopes (a 6SN7 for tube 11 and 12 is a 6V6). For a detailed discussion of PM counters see Tubes 1 to 10 are part of the clear circuits and have been described in section A.2.3, Tubes 15 to 22 comprise the transmitter circuits which transmit the sign indication over the add and suttr&oi titputs. Tubes 23 to 25 form a standard transmitter for the 1' pulse (used to give complements with respect to 10" instead of lflft-1, ^ere n is the setting of the signifi- cant figures switch.)
An odd number of pulses arriving at the Pii tirv-ry counter will ch-.nge its resulting position, /in oven number of puls-s will leave it the sane as it was to start with. If the number registered by the accumulator is pesitiv- :.rid an activated pro^riJii control has its operation switch set to AS then nine pulses will pass gste 15. If the registered number is minus then nine pulsus will be transmitted through gte 15 over the add output and none will go past gate 16.
Tjjffl$ L-tj
16
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; Pulse time ! 1 |
! | General i pulses |
Cycling i pulses | (2 1/2 ii | sec. lite) i |
Decide Registers |
j Pulses trans »over S?L !(subtrc&t) |
Pulses trans. over SH. (add) L |
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i .. 3 |
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CPP T- ■ i |
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RP |
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i i |
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i 2 |
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i io |
— i i |
10th |
3 |
l'P if dec;< . corresponds 1: St sig. figure |
ie to |
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i 1 1 ii |
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3 ; ! |
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3 ! |
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16 |
1 |
3 |
V - 1
V. THE HIGH SPEED MULTIPLIER
The high speed multiplier is a unit of the ENIAC capable of forning the product of two ten digit numbers in thirteen addition times (0.0026 sees.). It is called a high speed multiplier because, by making use of multiplication tables, it is able to produce a product much more- rapidly than if the method of repeated additions were used. In the method of repeated addition a maximum of nine addition times must be allowed for each digit of the multiplier giving a possible total of ninety addition times for a ten digit multiplier.
The method of multiplication used by the high speed multiplier is to multiply the entire multiplicand by each digit of the multiplier in turn and to sum the resulting products taking into account their proper decimal positions. Thus, only one addition time is required for each multiplier digit (plus three extra addition tines for operations that must be performed for each multiplication) #
The circuits are so arranged that the digit of the multiplier which is btdng used at a particular time excites a bus of two multiplication tables, a tens table and an units table. -The product of two single digits is usually a two digit number; thus, the output of the tens table is the tens digit of the products of the multiplier digit and the digits one to nine inclusive, while the output of the units table is the units digit of the products of the multiplier digit and the digits one to nine inclusive. The use of the tv.o tables makes it possible for the partial products to be received simultaneously into two accumulators without interference.
Since the product of two ten digit numbers is usually a twenty digit number it will be necessary to use two accumulators interconnected to form a twenty digit accumulator to receive the right hand (units) partial
products and similarly for the left hand (tens) partial products. Thus, for ten digit multiplication the high speed multiplier will work in conjunction with six accumulators, one for the multiplier, one for the multiplicand, two for the left hand partial products, and two for the right hand partial products.
Throughout most of the discussion of this chapter it will be assumed th?t accumulators 9 and 10 are used for the multiplier and multi- plicand, respectively, th=-t accumulators 11 and 12 (connected to form a twenty digit accumulator) receive the left hand products, and that accumula- tors 13 and 14 (also used as a twenty digit accumulator) receives the right hand products. The setting of the respective program controls on these last (two twenty digit) accumulators determines whether the final product appears in U and 12 or 13 and 14.
After the multiplying operation has been carried out for each digit of the multiplier (certain complement corrections may be needed) the right and left hand products are collected into one accumulator. In the fourteenth addition time (for a ten digit multiplication) the product may be transmitted to some other unit and simultaneously the multiplier and multiplicand accumulators may receive the next numbers to be multiplied. 5.0. INTRODUCTION. This description of the multiplier will be given in terms of the block diagram PX-6-308 and the cross section diagrams PX-6-112 r-nd PX-6-112A. In the upper left corner of the block diagram is seen the nultiplier selector. To the right of this (upper center) is the tens multiplication table and in the upper ri^ht corner is the units multipli- cation table. Below the tables arc the table gates which pass the 1, 2, 2', and 4 pulses. Below the gates are the two multiplied selectors, one for the tens table and one for the units table. The output of the multiplicand selectors goes to the shifters and thence to the digit outputs.
V- 3
These circuits comprise what will be called the numerical circuits.
To control the operation of these numerical circuits there ure the common programming circuits. The common programing circuits consist of the multiplier ring (located on the block diagram under the nultiplier selector), the round-off circuits (A' 46 to 49, A" to H* 45, and K" 45), the complement correction circuits (B" 46 to 50, C" 46 to 50, and L" 43 to 47), the receiving circuits (H, J, and L 41 to 50), the product disposal circuits (Dn to J" 46 to 50), the clear circuits (A to L 11), reset circuits (to the right of the ring), and below the reset circuits a receiver to cause the product accumulators to receive the partial products end a circuit (A" 47 to 50) to c-use the collection of the ri^ht and left hand products.
There remains tht pror?rara control circuits. These consist of twenty four transceivers, their associr.ted switches and buffer tubes. Associated with each transceiver we have the following switches: a) places switch, b) multiplier ?»nd ntultiolieand cle^r switches, c) significant fibres switch, d) multiplier receive switch, e) multiplicand receive switch, and f) the product disposal switch.
The program control circuits, the coranon programming circuits, and the numerical circuits will be described in detail in the next three sections. The fourth section will be devoted to examples. 5.1. PROGRAM COITTROL CIRCUITS.
5.1.1. The buffer plug-in units, hs shown in the block diagram there are two buffers on the progr-m input lines to each transceiver. There are ei*ht transceivers located on each of the three p-ntls of the multiplier. Thj sixteen buffers for each panel are located on two plug-in units. The tubes in these plug-in units are numbered from 61 to 68. Note that tubes 61 and 62 ar« associated with the first pro^r'^m circuit. Those numbered
v- u
63 and 64 would be associrted with the second program circuit and so forth. This buffer system aeana that at most five program controls need be us*d in each of the multiplier and the multiplicand accumulators in order t: rrc-ive the multipliers and multiplicands for all possible multiplica— ticr.s.
A program pulse arriving on terminal li, for example, would turn the buffers 61 and 62 en giving a negative pulse at the receive switches (see 5-2,3). Depending upon the setting of these switches pulses cay be obtained out of one of the terminals 1^ to Re and one ef Da to De.
5.1.2. Transceivers, These transceivers are standard, that is, they are identic! with th2 transceivers us^d in the sccumulators, the function tables, the divider, and the constant transmitter. This simplifies the problem of m- intidning operation, since, if :ny one fails the unit can
be pulled out and a sprre put in,
5.1.3. Progr :i coatrol sv.ii.cVs. With each transceiver there are the following switches:
a) Places switch. This switch determines how many digits of the multiplier art. used in the multiplication. S:nce the tine required for a multiplication is n+3 where n is the number of digits in the multiplier the tine required for a problem can be m: t>_rially short :ned if fewer than ten digits of the multiplier can be used. With the place switch setting at 8 (ds illustrated) the multiplier ring will step to stage 10 using eight di-its of the multiplier. The inverters G' U5 r-nd K' 45 being off the gate H» 46 will turn the inverter F' 47 =ff ""d °" the next addition time a CPP will pass gat.; F« IS and through the inverters C 47 and B« 47 will clear the rin<3 to stage 13.
t) Luitinlier i-nd ilultinlic-nd cli ar switches. Depending upon
V-5
the setting of these switches the following four possibilities arise:
'Ier Clear 'Icand Clear Result
Switch Switch
v1) ° 0 Neither multiplier or multiplicand
accumulators clear.
(2) C 0 An activated program causes inverter
J 30 to go off opening the gate H 30. This gate passes the CCG to the invert or G 31 which turns the buffer J 29 on. The output of J 29 goes directly to the dtir tubes. 2 to 10 in the PJ unit of the multiplier accumulator.
(3) 0 C In this e*se A 31 goes off opening
the gate B 31. The CCG turns off the inverter C 30 which in turn causes the buffer H 29 to conduct. The output of K 29 goes directly to the clear tubes of the multipli- cand accumulator.
U) C C Here the inverter E 30 goes off
opaning th* gates D 30 and F 30. ks sbove, the cle<r gate is passed into the two set3 of clear tubes in the respective RI units,
c) Significant figares switch. Depending upon the setting of the
significant figures switch a 5 is put into one of the decades of the left
hand product accumulators. If the switch is setting on 2 (as illustrated)
at the second addition time the digit 5 will be passed by gate HM L5
into decade mmber 8 of product accumulator nuaber 11 (corresponding to
digit output terminal SV ). U
d) Multiplier receive switch. This switch determines whether the multiplier accumulator receives the multiplier on the input terminals a, P, V, 5, or e. The program pulse arriving over li, for example, turns the buff.-r 61 on giving & negative pulse through the switch turning inverter H 46 off (if the switch is seating as illustrated). This causes the buffer H ^6 (these ar<- the two triod-s of a-6SK7) to conduct and the transmitter J to L 46 gives a program pulse out of the terminal R^ located
V - 6
on the front of panel one. This will normally be connected to the input of a receiver or a transceiver located in the multiplier accumulator and the corresponding program switch will be set to receive on e .
e) Multiplicand receive switch. This switch operates in a manner entirely analogous to the multiplier switch described above.,
f ) Product disposal switch. Suppose that the product is finally collected in accumulators 13 and 14. The setting of the product switch determines what the pair of accumulators (operating as a twenty digit accumulator) do with the numbers. Suppose the disposal switch is setting on SC (as illustrated). The program which started the multiplication set the flip-flop (66, 67 in transceiver) and so opened the gate 62 in the transceiver. At the end of the multiplication the reset signal arrives, passes gate 62 and turns off the inverter 65. This turns on the buffer 63 giving a negative gate through the disposal switch turning off inverter E" 46 opening gate E" 47. At the beginning of the next addition time a CPP is passed through the transmitter E" 48 to 50 to the terminal SC on front panel number three. Generally, the operator will connect this output to the input of a program control circuit on accumulators 13 or 14, say, and the corresponding program switch will be set to S and the clear switch to C
If needed, the other outputs A, S, AS, AC, and ASC, can be connected to the inputs of program control circuits on accumulators 13 and 14 (or 11 and 12 if the product is collected here) and the .corresponding switches set accord- ingly.
5.2. CCtfllON PROGRAMMING CIRCUITS.
5.2.1. The multiplier ring. This is a fourteen stage ring which controls the timing of the multiplication process. Whenever a program control circuit is activated the inverter H' l*U goes off opening the gate F' UU. This gate then passes central program pulses thr ^u.-h the pulse standardizer E« to B' UU t) step the ring. Whenever the ring is not at stage one the gate J» uu is open. This passes centr-.l pr.grim pulses to the inverter H' Uk and thence to the gate G' hh. If the initial clear gate is on the CPP pass G* Uk and step the ring until it arrives at stage one.. When
V- 7
it riches stage one J» 44 closes shutting off the CPP.
This method of initial clearing by stepping the ring to stage one is used here since, as described below, the regular clearing circuits y? rtft in conjunction with the places switch to clear the ring to stage 13 :•• the process of terminating the multiplication.
Suppose that program control 1 has been activated. The multiplier ring steps (at the end of the next addition time) to stage two- turning A» . 45 on and the inverter B1 45 eff . This opens the gates A1 46 and 47 which pass the 4 pulse s and the 1: pulse to give a five in some decade of accumulators 3 or 4. The output of 3- 45 also goes to gate B' 47 which gates a 1 pulse. This 1 pulse turns the inverter B' 48 off and thence sets the two receivers. The outputs of these two receivers come to front of panel three. (See PX- 6-304 ). From there these gate signals will be taken by special interconnecting jumpers to inter connector terminals ST, 1 on accumulators 11 and 12 and accumulators 13 and 14. Inspection of the accumulator block diagram PX-5-304 shows that this will cause the product accumulators to re-co.ve the D'-rtial products over the input digit terminals a . This is an example of a receiver located in one unit operating the governing circuits of another unit.
The timing is important here: Pulse time 17 18 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CPP steps S 1 P sets 4 P 1' P
ring to receivers start arrives second to cause stage partial prods, to be received
Thus, in one addition tine the ring steps to the second stage, the product accumulators are set to receive, and the five pulses for the round- off are put into the proper decode. The CPP that steps the ring could not be used to operate the receivers because of tht time it takes for B' 47
V - 6 to open*
The next addition tine the ring steps to stage three. B' 42 goes on and inverter L 1 off opening the gates for the tenth digit of the multiplier (gates K 2 to K 11). Depending upon the tenth digit of the multiplier one of the lines through the multiplication tables will cf-rry a negative gate (which will turn off certain pulse gates). At the sraae tine inverter E' 41 will go off causing the bottom row of gates in the two shifters to open. Thus, the tens partial product will feed into accumulator 11 and the units p rtial product into decades 1 to 9 of accumulator 13 and decade 10 of accunul?tor 14. Notice that the units product is already shifted one place to the right. Thus, when the right and left hand products are collected at the end of the multiplication no extra shift- ing will have to be done.
As the ring steps from 3 toward stage 12 the gates for successive digits of the multiplier are opened and the gates on corresponding levels in the shifters are opened.
If the place switch is setting on 8 the inverter G' 45 is off opening gate H» 46. Vflien the ring reaches stage 10 the inverter H' 45 goes off causing the gate H' 46 to go on and the inverter F« 47 to go off. This opens the giAe F' 48 and at the end (pulse time 17) of the addition tine a CPP turns the inverters C» 47 and D« 47 off clearing the ring to stage 13 (this clear signal overrides the stepping signal which would normally step the ring to stage 11). The output of F« 47 also gates a CPP at the end of the addition tine at E! 48 which turns the inverter F» 49 off causing the receiver flip-flops to reset. This causes the product accumulators to stop receiving the partial products. The out- put cf Ft tf also opens the gates B" 46 end L« 47. The CPP gated by B" 46 ultimately gives a program pulse out RS if the multiplier is negative and out DS if the multiplicand is negative. If both multiplier
7-9
and nultiplicand are negative L" 47 gates a l! pulae which finally goes into the Ftf channel to accunulator 13.
'.."hen the ring steps to stage 13 the inverter L' 45 goes off and rt.s D 49, K" 50» and A- 47 are opened. At the Hth addition time J ^9 gates a CFP which sets a flipflop causing progroas 1 to 8 to re- set. «t the sane tine K" 50 likewise ceuses prograas 17 to 24 to be reset. «" 47 gat^s a CF? during the 14th addition tine which will generally be used to collect the right and left hand products. This pulse is transmitted to teminal p on the front panel. Fron there it will be junpec: ty the _perat;r to a. pr-gran traj and then used to progrca trans*- nissi r. of the left hand partial predict, sar, ind the reception of this i-ft hand product ty accumulators 13 and 14.
Store 14 'f the ring causes programs 9 to 16 to be reset. The ring is located en panel two cf the multiplier, so the g^-tes 62 in transceivers 9 to 16 can be rp*_rated dir ctly ty the output of the ring. Since transceivers 1 to 8 are or panel one a special flip-flop (I and ? ..7} set fey % Cr? -orir.- the 13th aoliti,n tin- (passed ty gate Z Jr »r-ich is reined by stige 13 if the ring) pro-?ides the rsset signal, Sirilarl-, en.ther flinflr (1* ani £* 49) resets programs 17 to 24*
Free stare It. the rinr st-es tack t"^ st'ge 1 and st^ps. At
The initial cie~r -sate is a-nlSed t- the nultiili^r ^ly tfcrai^b 3* _. This gate is -nen valy wnn the pris^-as ring is be* vc stag* Tn_5 f- eff-«a -.f -.—-Trio- fcjjg ini-.i-i clear is t, ca.-t-s tee pr-jgran. fct step srooad t- stage aae sad r.;..
In the case -f te ra.lt inll-r prvgrsa rlag S*e st'-ssfeetf netted .eariar ii ,K- f r garter torp-v.. £!=*« -■'■• aaabas- -f p2a**a rf tZzzzZLa* xtett is Bffl£4* *a-l vary fr a ~..~- f '" <T« - '-— ^'--
V - 10 between the setting of the places switch of an activated program and the stage on which the ring is setting will open gate F'48 causing the ring to "clear" to stage 13.
ks with the accumulators there is no need to initially clear thfc transceivers. Any program pulses which get started in the programing circuits are allowed to run through the sequence (all sequences are broken at the master programmer, see 10.5), and then the decades of various units are cleared.
5.4. NUMERICAL CIRCUITS.
5.4.1 The multiplier selector. The multiplier selector is an array of one hundred gate or coincidence tubes. There is a tube for each possible digit in each place of the number. */hen the multiplier ring is at stage three the gates for the tenth digit of the multiplier will be open. If the first digit of the multiplier is 4, for example, then the static output of that st-ge of the tenth decade of the multiplier accumulator will be energized and the tube K 7 will conduct giving a negative gate to the inverter L 7. When this inverter goes off the tubes L 26 and K 26 go on giving a negative gate on line 4 into the multiplication tables.
5.4.2. The tables and the table gates. The 1, 2, 2«, and 4 pulses come fro the cycling unit trunk to buffers D 45 and 47 and E and F 48. Fna the buffers each pulse goes to an inverter and then to the table gates. Inspection of the cross section PX-6-112(a) shows that the table network is such that normally the second grids on the table gates are sufficiently positive that they pass the 1, 2, 2' , and 4 pulses. Thus, the multiplica- tion table is a so called »c implement ary" table, that is, all the gate tubes nrmally pass the 1, 2, 2' and 4 rmlses and arc turned off by the table if they are not wanted.
The digits of the multiplier arc represented by the horizontal
V - u
lines through the table. The digits of the multiplicand are represented by the vertical groups of lines as labeled at the top of the table. In nultiplying one tines nine (consider one as the multiplier) the lines of the l'.st column of the units table have nc connections to the horizontal
. 1. This allows gatss D to G 21 to pass nine pulses which is : •.. units psrt :>f the product of ni.ne and one* In the tens table for the sane two rubers there ar*- connections to all four vertical Lines. This neans titst gates D to G 41 will be closed, which is correct since the tens part of the product of 1 and 9 is 0.
New, consider six times seven. On the horizontal line for six in the units table in the column for seven there are connections to 1, 2', and h but none to the 2 lines. This means that gate F 23 will be open and will pass two pulses but D, E, and G 23 will be closed. In the corresponding place in the tens tjble there are connections to the lines for 1 and 2. Therefore, the gates E and G A3 will be closed while D U3 will be open and will pass U pulses. Notice that zero in the nultiplier must be c-jnnectecL to aLL vertical lines in the table so as to stop all pulses frou going to the multiplicand selector. Also, note that zero gates are not needed in the multiplicand selector.
5.^.3. The multiplicand sel ■» ofcors. The output of the table gates for the nine column in the tens table goes to the top row of gates in the left hand multiplicand selector. The output of the eight column goes to the second row, and so forth. There is no need for a units column or a units row in the tens selector since one times any digit gives zero in the tens place. Similarly, in the units table the output of the nines column goes to the top tjw af the selector, et cetera.
Suppose the digits f the multiplicand arc 98765 43210 and the multiplier digit is six. In the tens stlector gates L« 21, K' 22, J« 23, ..., D» 28 will be open and will respectively pass 5, U, k, 3, 3, 2, 1, 1
V -12 pulses. In the units selector gates L' 1, K' 2, J' 3 ,,., C« 9 will be open and will respectively pass 4, 8, 2, 6, 0, 4, 8, 2, 6 pulses. These pulses will feed through a invert er-buffer-inverter sequence into the shifter. If the six was in the third place of the multiplier then th« • t.s H» 30 to H" 21 and H" 10 to H« 1 will be open in the respective lifters. Thus, the partial products of this step in the multiplication will arrive in the product accumulators in the following manner:
Ace. 1L acc. 12 Ace. 13 Ace. 14
OOCX 00544 33211 00000 00000 00048 26048 26000
The output of the shifter passer: through the driver tubes (a" to K" 44, for example). This is quite different from the standard transmitters used on the output of an accumulator (see PX-5-304) . . This means that for reliable operation the product accumulators should be close to the multi- plier and a short tray with no load box used to cerry the partial products to the accumulators.
With the interconnect or cables in use at the present time the partial products are received over the a inputs to the accumulators. Since the capacity on the outputs of the driver tubes mentioned above is limited (for the capacity LLrAts here see the operators manual), the a inputs to the accumulators u^-d to receive the partial products must not be used for any other purpose.
Note that rows of shifter gates are opened only when the program rinp; is on stages 3 to 12. Thus, when not multiplying (program ring is at sta^e 1) pulses (passed by the table sates ^d the multiplicand selector) are not passed by the shifter gates.
V - 13
5.5. EXAMPLE,
Addition arid Dulse tine
0.17
1.17
2.1
2.6
to
2.10 2.17
3.17 4.17
Operation of multiplier.
Description
Program pulse arrives at transceiver. This pulse passes buffers (61 and 62, for example) and depending upon the setting of the multiplier and multi- plicand receive switches may be transmitted again. Gates F'44, K'46 and K" 45 (assuming the places switch is at 10 and that the significant figure switch is at 10) are opened.
A CPP Gates
passes F'/ytj- v» 1,6 and 47
to step the program ring to stage 2. are jpened, as is gate B'47»
One pulse passes gate B'47 to set the £ and r receivers. Four pulses and a one primed pulse pass gates A' 46 and 47 to give five pulses out channel 10 of S7
The program ring steps to stage 3.
The output of stage three causes the multiplication of the
multiplicand by the first digit of the multiplier to take
place.
The program ring steps to stage 4 and multiplication by the second digit takes place.
The progr urn ring steps to stage five, and so forth.
11.17
12.10
12.17
13.17
14.10
The program ring steps to stare 12, opening gate P'48, E'43, B"46 and L"47.
Uultiplication by the tenth digit of the multiplier takes place .
l'P passes LM47 and (if both multiplier and multiplicand are negative) will be transmitted into the PM unit of accumul&tor 13.
a CPP passes F'48 clearing the ring to stage 13 opening rates D49, K"50, and a"47. » CPP Passes E»48 to reset the 1 and r receivers, a CP? passes gate B"46 and m&y pass B"47 and/or Cn47 to cause the complement corrections.
The program ring steDs to stage 14. CPP pass gates D49 and K"50 to set the flip-flops E, F49 and K», L"49. a CPP passes gate ~"47 to be tr-nsaitted to program the product c:ll-cti n (this oulse appears at terminal F).
The CCG mav pass one or two of the gates B,D,F, or H 30 to cause the multiplicand and/or the multiplier accumulator to clear.
u
H.17 CPP pass pate 68 in the activated transceiver to reset
it and to (jive an output, r.rogram pulse. A CPP may p'-ss one of the gates D-' to J" tf to program the product disposal. The prc.rran ring steps back to stage 1.
VI
VI. DIVIDER AND SQUARE-ROOTER
The divider and square-rooter performs the operations of dividing and square-rooting ten and twenty digit numbers. To carry out these operations with ten. and twenty digit numbers it makes use of four and seven accumulators, respectively. Thus, the divider and square-rooter unit itself is essentially a programming circuit which controls the operation of the associated accumulators.
The process of division is that of repeated subtraction. Thus, the numerator is in one accumulator and the denominator in another. The denomiiistor is subtracted until an overdraft occurs. At this time the numerator is shifted (by transmitting to a shift accumulator and transmitting back with a shifter in the digit line). Note that the overdraft was not corrected as in some methods of division used on computing machines. Instead, signs are changed and the denom- inator is alternately subtracted and added between the shifts. The quotient is built up by the divider sending ♦! or -1 into the proper decade of the quotient accumulator for each subtraction.
The process of square rooting is likewise accomplished by repeated subtractions (the quantity subtracted being increased by two each time in the proper decade). The number to be square- rooted is placed in the numerator accumulator and the numbers to be subtracted are built up in the denominator accumulator. When an overdraft occurs the number in the numerator accumulator is shifted (similar to the shift in dividing) and certain corrections are made to the number in the denominator accumulator and the subtraction process is repeated. As the process continues twice the square root is built up in the denominator accumulator.
VI - 2
6.0. BJTRODUCTIOH
Description of the divider will be given in terms of the block diagram PX-10-30^. For purposes of description the circuits of the divider square-rooter will be divided as follows:
1) Prot-T3n controls. The program control circuits consist of eight transceivers and their associated switches. These switches and their purposes are as follows;.
a) Numerator receive switch. During the first addition tine of the division this switch may be used to cause the numerator accumulator to receive either a or P.
b) Denominator receive switch. During the first Addition time of the division this switch may be used to cause denominator accumulator to re- ceive on a or 0.
clear
c) ilui-ntor switch. At the end of the division or root process
A
this switch may be "Led to cause the numerator accumulator to clear.
d) Denominator clear switch. At the end of the process this say be used to cause th< denominator accumulator to clear,
e) Interlock switch. This switch decides whether or not the interlock feature is used. Suppose this switch is setting on ?II. At the end of the division or root process the various flip-flops and rings in the divider square-rooter are cleared and an output program pulso is transmitted. If this snatch is on I then this clearing process and output pulse does not occur until toth a signal is received on one of the interlock inputs, (upper left corner of PX-10-304), and the division or root process is completed.
f ) Answer disposal switch. This switch is connected to four receivers and thus gives four possible ways of disposing of the answer (that is,
VT - 3
four ways it could be transmitted).
g) Round-off switch. This switch decides whether the answer to the division or the square rooting process be rounded off.
h) Division-Square root and place switch. This switch determines whether the process is division or square rooting and how many places are used. There is a choice of L, 7. 8, 9, or 10 places.
2) Tho common programming circuits. In the divider-square rooter
(as in other unit?;) +he conmon programming circuits comprise all of the circuits except the program controls (described above) and the numerical circuits (described just below).
3) Numerical circuits. The numerical circuits of the divider-square rooter comprise the place ring and its associated gates (lower right hand cornes of PX-10-304), the pulse gates (just above and to the right of the place ring), and the "1", n-V*3 '■?", and ,l-2!' receivers which open these gates.
6.1. PROGRAM C0!n?0LS
There are 'jight .standard transceivers to receive the incoming program pulses. As in the case of the multiplier the incoming program pulse is immediately retransmitted to cause the numerator and denominator accumulators to receive their numbers vithout the loss of time. This retr-uismis3icn takes place through buffers located on a separate plug-in unit (there are two such plug-in units altogether). Two such buffers, 67 and 68, are illustrated in the lower left comer of PX-10-304, 6.1.1, Numerator and denominator receive switches
The buffers 67 and 68 (described above) feed two switches located on the front panel, namely, the numerator and denominator receive switches. Each
?I-4
of these switches have three settings, a, 0 and 0, The four outputs of these
two switches go through inverters (BA, B5, A4» and A5) to four receivers (located
on two plug-in units). The outputs of those receivers come to output sockets
located on the front panel. The outputs may be connected directly to the common
programing circuit a of the respective accumulators by use of a -^p.eeiil inter-
conns jtor reble ^See ssntiJE 11.6.4.).
6-2 .2. The nuncrat ox^ ane1 Jimominator clear switches
The oot*-.rt rf r«ie of the buffers 63 (in the -.ra;;sc-:iv j~) roer to the
Eirrerator -ir.d denominafcjr rlear switches. This buffer ^>3 gess '.-r. only at the
Bad of the division or rooting process (and possibly after" an interlock signal)
wht-n clearing is tckirg place. The output of the switches (three outouts:
nurerator, den.^ninaooT, cr both) goes to inverters CU^ r~.d u.V? ^nd i hence to
gates A£. :-L$. Bv*. cij 3.-?. These gates pass the carry cl«sx gate (CCG)
through ih^ iinre-ters «/," .-.rd/or B47 and buffers a46 ar.d/or 3^6. This signal
goes dij*ect>y-ta tire c^ar- tubes in the PM-Clear units of the corresponding
accumulators ;se<2 PX-*-jC7.i« The following table illustrates what happens
with the various :>e'.-tJLi£S of these switches:
TABLE 6-1
Nun. Clear Denes*. Clear Effect
Switch Switch (as tube 63 in i« nsceive*- goes or)
0 3 Konn
C 0 D49 goes off and gate Big passos a CCG through
the inverter B/»7 and buffer B46 to the clear tubes in the numerator accumulator.
0 C Half of C49 goes off end gate A49 passes a CCG
through A47 and A46 to the clear tubes of the denominator accumulator.
C C The other half of C4? goes off and gates A48
and EA9 pass CCG' s through kU7 and A46 in one case and B47 and BA6 in the other.
VI -5
6.1.3. Interlock Switch
The setting of this switch determines whether the tutecLoefc feature is used or not. If this switch is setting at "NI" the buffer 61 (in the trans- ceiver) causes the inverter L49 to go off and the gate K49 to open. The CPP's passed here turn tfe? inverter H49 off. The gate H50 is opened at the end of the division or square rooting process and the CPP»s from H49 are passed to provide the clearing ac|icn.
If the interlock switch is setting at "I" the other half of L49 is turned off and U& is open. In order for a CPP to get through to gate H50 the flip-flop H, J 48 nust be set opening gate J49. This flip-flop is set only when a signal arrives over one of the interlock inputs turning on one of the buffers F 46 to 48 or G48. (This pulse nay arrive during the division or root process or even before it starts).
Thus, if the switch is set on "I" the clearing signals and the output program pulse are not provided until; (1) the division or square rooting process is completed and the control ring steps down to stage seven, and (2) a program signal has arrived over cne of the interlock input terminals and set the flip-flop H, J48. Note that the interlock flip-flop H, J48 is not reset unless the program control being used is set to "I", This means that a number of divisions or square roots nay be done and then the interlock feature be used at the end even though the interlock pulse arrived during one of the earlier divisions. 6.1,4. Answer disposal switch
This switch has five positions, four of these go respectively to four receivers and the fifth is an "off" position. At the end of the division or square rooting process (and ^fter the interlock signal has arrived if the interlock switch is at "I") the buffer 63 (in the transceiver) goes on. This
VI -6
nay (depending upon the setting of the switch) cause one of the inverters E46 or &7 to go off opening one of the gates C or D 46 or 47» The CPP passed *r one of these gates will turn the corresponding inverter C or D 48 or ft$ off activating the corresponding receiver. The outputs of this receiver go directly (provided the operator connects them) to the common programing circuits of the quotient accumulator or to the denominator accumulator depending on the inter- connector cable used (see section 11.6.4.) The timing of the operation of these *' circuits is explained in sections 6.4.L and 6.4.2.
6.1.5. Round-off Switch
The round-off switch is a double-pole, double-throw switch which determines whether the answer is to be rounded off or not. One pole of the switch operates in case of division and the other in case of square rooting and works in conjunction with one deck of the root-divide and place switch. The four terminals connect to four inverters (the four triodes of L4 and L5) which in turn connect to the gates L3, K3, K4, K5, K6, and L6. These gates provide the division pulse (DP), the square root pulse (SRP), and the round-off pulse (HOP).
6.1.6. Root-Divide and Place Switch
Of the two decks of this switch one (the one on the right on PX-10-304) determines whether the process is to be division or square rooting. This deck takes the output of buffer 61 in the transceiver to the round-off switch described above. The other deck determines how many places the answer is to contain. This • switch handles two jobs. This means that the number of places used in a division or a square rooting is restricted to 4, 7, 8, 9, or 10.
VI - 7
6.2. THE COMMON PROGRAMING CIRCUITS
The common programming circuits, which constitute most of the divider, will be divided into sections as indicated below. This subdivision is a logical one, that is division is with respect to the purpose of the particular circuit and not with respect to physical location. To a considerable extent this division is indicated on the block diagram- PX.1&.304 by the spacing between circuits. The subdivisions ape:
s) The pulae source circuit. This circuit centers around the pulse soaxe flip-flop E 4 and 5 located to the right of the program control circuits an. the block diagram. The circuit extends up to and including the gates L3, K3 to E6, and L6.
b) The program ring circuits. The program ring is located on the upper left portion of the block diagram. This circuit includee the program ring flip-flop A, B 6 and the associated gates.
c) The sign indication circuit. This circuit (located in the upper right hand corner of the block diagram) includes the denominator flip-flop, the numerator ring, and the sign indicating matrix (just below).
d) The over-draft circuit. This circuit determines when the numerator changes sign, that is, when there has been an overdraft. This circuit is located at the top center of the block diagram.
e) The add-subtract circuit. This circuit programs the trial additions cr subtractions and is located directly under the numerator ring and the sign indication circuit. Its left hand part consists of the Nft receiver and the Dy
ad Qy receivers. The right hand part consists of the Dg and DA receivers and the associated gates, inverters, and buffers.
VI - 8
f ) The round-off circuit. The round-off circuit is located practically in the midst of the add-subtract circuits. It consists of the round-off flip- flop L 11 and 12 and the associated gates and inverters. It includes the gates G8, H8, E13, and F13.
g) The root correction circuit. This circuit is essentially the receiver D and the root reset lines.
h) The shift circuit. The shift circuit is below the overdraft circuit and to the right of the pulse source circuit. At the time of over-draft it causes the number in the numerator accumulator to be transmitted to the shift accinulator and then to be transmitted back again. A shifter is used on the input (a) to the numerator accumulator so that the number is shifted one place to the left when it comes back from the shift accumulator. The shift circuits comprise the S^ N^, SA, and Ka receivers and their associated gates and in- verters.
i) The clear and interlock circuits. The clear circuits are locate* in the upper left hand corner of PX-10-304 to the left of the program ring. These circuits determine when the division or rooting process has finished and (depending upon the setting of the interlock switch of an activated program control) perhaps when some other sequence of computations is finished (as indicated by the output program pulse of that sequence arriving over one of the interlock inputs). Since a division or root process is of unknown length this allows the operator to carry on other conputc-tions simultaneously and then to follow with another sequence of computations only when both the division or root process and the other sequence are completed, 6.2,1. The pulse source circuits.
The pulse source flip-flop is normally in a state which causes gates
VI - 9
F4 and F6 to be open. The flip-flop is in this position aoccept for period III (see PX-IO-3O5 or PX-10-306, the division and square rooting time tables). Thus, duing periods I, II, and IV central program oulses pass gate F4, go through the inverter G4 and the cathode followers G3 and H4. This produces a general pulse (GP) which does the following things
(1) goes tc gates K6 and L6 to produce a division puiae (IP),
(2) goes to gates L3 and K3 to produce a square root pulse (SRP),
r
(3) goes to gate A7 to clear the program ring,
(4) goes to gate B7 to set the program ring flip-flop,
(5) goes to gate D9 to produce a "P" pulse which causes an add- subtract cycle to take place (see the time tables PX-10-305 and PX-10-306),
(6) goes to gate E9 to cause a shift cycle to take place,
(7) goes to gate Cll to produce a root reset pulse,
(8) goes to gate C9 to produce a WP" pulse which starts another add-subtract cycle after a shift cycle is completed, and
(9) goes to gate D6 (top of drawing) to step the numerator ring and set the denominator flip-flop in case of negative signs.
The gate F6 passes the one-primed pulse and during a shift cycle this pulse passes gete L45 to step the quotient place ring. Using the l'P here allows extra time for the quotient ring to step and set up its array of gates.
buring period III the flip-flop E 4, 5 is set. This opens the gate F5 and the central program pulses pass the inverter G5 and the cathode follower A12 to produce a third period pulse (HIP). This third period pulse does the following things:
VI - 10
(1) goes through the buffer C12 and the inverter D13 to give a root reset pulse,
(2) goes to the gates K4 and K5 to produce a round-off pulse (ROP),
(3) goes through the buffer and inverter A12 and the buffer A13 to the t pulse standards zcr of Ihe program ring.
The pulse source flip-flop is set during a shift sequence by a pulse , passing gate E6. This gate will be opened by the inverter D50 going off, and j this is caused by a coincidence between the setting of the place switch and the : position of the quotient place ring as detected by one of the gates A to C Id, A42, or AA3# This flip-flop is reset either by the program ring reaching stage seven and opening gate F3 to pass a CPP or by a CI' pulse arriving at the buffer F3 from the clear circuits. The Cl« pulse resets this flip-flop when initially clearing whereas the CPP passing E3 indicates the division or reoting is completed and by resetting E4, 5 prevents the program ring from stepping until A, B, C i» reset and another program control is activated. 6.2.2. The program ring circuits.
Normally (after initially clearing) the program ring flip-flop (A, B 6) causes the gates A10 ard All to be open. Thus, as the process of division or square rooting starts the DP pulses or the SRP pulses pass one of these gates and (going through the inverter A12 and buffer A13 to the pulse standardizer) step the program ring. In two addition times (see section 6.^.1.) the program ring will step to stage one. The output of this stage opens gates A7 and B7. A7 passes a general pulse (GP) which turns off the inverter A9 clearing (the clear signal overrides any stepping signal) the program ring back to stage one. At the same time a GP passes gate B7 to set the program ring flip-flop (A, B 6). This closes the gates A10 and All preventing the division pulses (DP) or the
VI
square rooting pulses (SRP) from stepping the program ring again. After this tha program ring remains in stage one until the third period pulse (IIIP) is produced. Ibe IIIP will then caise the ring to step through ?11 nine positions.
The 'pofdticas o" o',e program ring at all times is listed in the division and rquexs rootlig times tables PX-10-305 and PX-10-306. The follow- in? tabla gi-'t-s thj efio-r. af each position of the program ring.
TABLE 6-2a
Period I
Position of zrogran ring
Division
Gate D« if: opened to pass a general pulse (u?* through the inverter D5 to the gates Kl and Bl to set the num ±1 utor binary ring and the denom- inator flip-flop in case of negative sigrs,
(1) Cpens gates a7 and B7 to clear program r:;g and to set the program -in," flip-flop. This causes the ring - c rle x co zero and remain there until ptriod III.
(2) Cp-rs gate B8 which passes a divl'si** pulse (giving a P pulse) starting the first add or subtract
gqu&rg rooting
Same as for division.
(1) Same as for division.
(2) Opens gates K8 and C7 . Thess pass square rv-o^ing pulses (SRP) v?hi'"h c.-iusa +1 to be placed in the denonina^ tcr accumulator to start the square root process.
VI - 12
TABIZ 6-2a (Cont'd.)
I Pes; tior of j pro.fr in ring
Period III
(.Operation is same in division cr square rooting)
0pe..3 jate C8 to pass a round-off pulse (ROP) giving a f pulse which starts the add or subtract process, Geoe LG is opened but with no effect since general pulses »G?; -vre not produced in this period, 1
No effect since GP, DP, or SEP pulses are not produced tboc otriod.
Cc.r? gate DA to pass an ROP giving a reset pulse which t-e^-nioutes the add or subtract process started above.
Cp=ns gate J13 passing an ROP through the inverter K13 to gate K12. In case of no over-draft K12 passes this pulse through the inverter KH into tnc round-off circuits.
Opens L 50 which passes a CPP to the clear circuits and opens E3 resetting the pulse source flip-flop.
£.2.3. The Sign Indication Circuit
In division this circuit (which consists of the gfit'-fi Bl, C, Il> the flip-flop C 1 and 2, the binary ring H 1, 2; and tho ma* rix of gates Dl, 12, El, E2) detects the initial signs of the numerator and denominator and, thus, determines whether the denominator is to be added or subtracted and whether ♦1 or -1 is to be put into the quotient. In the cesu of square rooting, after the process is started these circuits serve exactly the same purpose as in
VI - 13
division; that is, after an over-draft the arithmetical process must be changed from addition to subtraction (;r vice versa) .and the sign of the twcts added irr.o *.he denc'ii-na^or ac ;\*nr.j3tor must be changed*
In peri-.-d i ti s,ao process (division o?" square rooting) ii« ^ate D6 i., cpcr.jd ay the. pr;j-.:i a-j ring s tapping to stage B«
If the den t'- v:t->r is negative, the negative static output of the Pi-Clear unit of the dstjoiExnai.or accumulator causes gate PI *.o open. If the nuaerator is negative t..- static output of the negative stage of the JU ring of the numerator accumulator causes gate Kl to open. Thus, when the program ring steps to stage B a general pulse (GP) passes gate D6, turns the inverter L> off and may pass gat^s Bl and Kl (depending upon the signs of the numerator and denominator).
Thus, after the program ring has reached stage B there are four possible situations d, illustrated in the following table.
TABLE 6-2b
|
Kuner at or |
Line-air. -j. '.or |
Matrix |
ftcsult |
|
Sisn |
Sign |
Fate on |
|
|
♦ |
+ |
El |
' BIO, G8, E13 Br- c>en. BIO passes a pu-Lce v tr r.V sets the Dg receiver cauein- th«. c.. n.-jr^nator to be subtracted* |
|
* |
- |
Dl |
Bll, H8, F13 aro c>n ar-i d^ncainator will be added. |
|
- |
♦ |
E2 |
Bll, H8, E13 are open.. |
|
- |
" |
D2 |
BIO, G8, E13 ar- op.n |
VI - u
Nate that the arrangement of the gate tubes in this circuit is not the usual plan followed elsewhere in the ENIAC. Usually, there is an inverter between two gates. If the first gate tube begins to conduct it causes the I inverter to go off. The resulting positive signal causes the second gate tube I to conduct (assuming the other control grid is sufficiently positive). Here . in the sign indication circuit (the same is true in the overdraft circuit, see section 6.2.A.) there is no inverter between the gate tubes. The plates of El
and D2 are connected to one control grid,, of the gate tubes Bll, H8, and F13, Thus, if gatu El or D2 is conducting the grids of the three gates are held below cut-off and none of them can conduct* On the other hand, if neither El and D2 are conducting then their plate potential is relatively high and the gates Bll, H8, and F13 will conduct if a relatively positive signal is applied to their other control grids.
Note that the denominator flip-flop is changed only at the beginning of the process, that is, it does not change its state during the process of division or square rooting. On the other hand, the numerator ring is stepped at the start for negative numerators and, in any case, is stepped during each shift sequence. At the end of the process the clear pulse (CI) arrives from the clearing circuits and resets the flip-flop and clears the numerator binary ring. 6.2.^. The over-draft circuit
The over-draft circuit is another matrix of gates similar to that in the sign indication circuit. This matrix is fed by the output of the numerator ring and by the static outputs of the M ring in the numerator accumulator. The setting of the numerator ring is fixed during the process of addition or subtraction (in both division and square rooting) and its setting
VI - 15
depends upon the original sign of the nuuerator and the number of shifts which have occured. When the Hi sign of the numerator changes indicating an over- draft the static leads to the overdraft circuit change their potential causing a different gate to conduct.
As explained in the next section (6.2.5.) the add-subtract cycle takes Uo addition times. Thus, there is a full addition time after each trial addition or subtraction for the PM static lines from the numerator accumulator and the over-draft circuits to set up.
Thus, the sign indication circuits remember the sign of the denominator by the denominator flip-flop (remains unchanged throughout the whole process) and the sign of the numerator (by the numerator binary ring) (changes after each over-draft); and the over-draft circuit detects a change in sign of the numerator (or radicand in case of square rooting)*
After the program ring has reached stage B (in period I), allowing the numerator ring to be stepped if necessary, gate G2 will be conducting if the numerator is positive. or else Fl in case the numerator is negative. Then gate D12 is closed and gate Dll is ©pen. Gate Dll being open leads to the production of a pulse P which causes the add-subtract cycle to take place. When an overdraft occurs F2 or Gl is conducting, causing gate Dll to close and D12 to open. This leads to a shift sequence, that is the numerator is sent to the shift accumulator and then transmitted back through a shifter which moves it one place to the left. 6,2.5, The add-subtract circuit
The add-subtract circuit consists essentially of five receivers and their associated gates and inverters. These five receivers are (1) DA which programs the denominator accumulator to transmit the denominator over its add
,.,,,.,.-,. I—,
VI - 16
output, (2) Ds which programs the denominator accumulator to transmit the
denominator over the subtract output, (3) ^ which programs the numerator
accumulator to receive on a (this receiver is on the gate chassis instead of
on a plug-in unit), (4) Q^ which programs the quotient accumulator to receive
on y, and (5) D which programs the denominator to receive on y. Receiver O
is used only in the process of division and receiver X> is used only in the
process of square rooting.
At the start of an add-subtract cycle a P pulse passes gate BIO or
gate Bll, turns off the inverter B12 or B13, and activates the D or the D.
S A
receiver, respectively. These receivers are reset by a signal from the buffer C5 or the gate D4. If the receiver Dg is activated the fast buffer output from a cathode follower goes (by way of interconnecting cables) to the common programming circuits of the denominator accumulator causing that accumulator to transmit over its subtract output. The slow output of the Dg receiver goes through the inverter Cll and opens the gates Gil and G12. The receiver DA operates in a similar manner causing the denominator to be transmitted over the add output of the accumulator and the gates Hll and H12 to be opened.
The same P pulse which causes the D. or Dg receiver to be activated also activates the 1^ receiver (C, D 7, E7, F7, D8). The output of the cathode follower F7 goes to the coaaon programming circuits of the numerator receiver and causes it to receive on a# The slow output goes through the buffer and in- verter E7 and 18 to *pen the gates L9 and L10.
L9 or L10 pass square root pulses (SRP) or division pulses (DP) which set the Dy or a receivers, respectively. The division pulse (DP) which passes L10 to set the 0 receiver also passes Gil or Hll to set the ♦! or the -1 re- ceivers in the numerical circuits (see section 6.3.) Similarly, in the process
-— — — — ~—
VI - IT
of square rooting the SRP which activates the IL, receiver also passes G12 or H12 to set the *2 or the -2 receiver ►
The slow bufTer outputs of the D and the Q receivers join and
y y
connect to the grid of the inverter CIO. Thus, when either D or 0 is activated
the inverter CIO will go off, the buffer E6 on, and the inverter F3 off giving a positive signal to the gates DLL and D12. If this addition or subtraction did not produce an overdraft gate Dll will be open, the inverter D10 will go off open- ing D9. This gate passes a general pulse (GP) producing another P pulse which starts another add-subtract cycle. If there has been an overdraft then gate D12 conducts st?xting a shift cycle (see section 6.2,8.) 6,2.6. The round-off circuit
The round-off procedure consists of subtracting the denominator from the numerator five tines (in the case of square rooting, twice the square root is subtracted five times from what remains of the radieand in the numerator accumulator). If there- is en over-draft nothing is done. If there is no over- draft then, depending upon the signs and whether the process was division or square rooting, a +1, -1, +2, or -2 is added to the quotient or to the denomina- tor (twice the square root).
The round-off procedure occurs during period III (see PX-10-305 and PX-10-306) which is inaugurated by coincidence between the position of the quotient-place ring and the position of the root-divide-places switch as detected by one of the gates Ml, BU, CU, A42, or kU3, The subtraction (or addition) is started by a round-off pulse (ROP) being gated by C8 when the program ring is at stage B. This activates the Ha and the DA r Ds receiver (the Q^ or Dy and the +1 or ±2 receivers are not activated since no DP or SRP pulses are produced in period III). Since general pulses are not produced in this pericd, the DA or Ds and the N receivers are not reset until the ring reaches stage 5.
At that tine a reset signal is produced by an ROP pulse being gated by D4. flhen the program ring reaches stage 6 an HOP pulse is gated by J13, and if there has been no over-draft this pulse is passed by gate K12,
The divide-froot flip-flop remembers whether the process was square rooting or division and accordingly decides whether to send -1 or ~ 2 and whether to send then to the denominator accumulator or to the quotient accumula- tor.
In case of division the pulse which may be passed by gate K12 passes g^te J10 to set the Q receiver and it passes gate J8 to activate the *1 or the -1 receiver (depending upon the signs this pulse may pass gate G8 to activate the *1 receiver or else it would pass the gate H8 to set the -1 receiver). 6.2.7, The root correction circuit
In the process of square rooting, after an over-draft has occurred it is necessary to correct the number appearing in the denominator accumulator. In the case of a subtraction cycle the number being subtracted (that is, the number in the denominator accumulator) is being increased by two each time. After an over-draft occurs one more two is added on, then one must be subtracted at the sane place and another one must be subtracted in the next place to the right. If it is an addition cycle, then two is being subtracted from the nunber in the denominator each tine, and after the over-draft one more two is subtracted, then one is added on and another one added in the next place to the right.
The circuits are so arranged that there is always one more "two- added or subtracted after the actual over-draft occurs. The root correction circuits take care of the adding or subtracting the "one".
VI -19
After an overdraft occurs a general pulse (GP) passes gate E9 starting the shift process, sotting the flip-flop (*., F 10) of the DJ, receiver, and passing gate H9 • r C-9 to set the ♦! or the -1 receiver. These receivers raiair. activated for two addition tines, since the root reset signal is not produced until the IV y receiver is set, opening gate Cll. The quotient place ring is wfc<rnfcic*lly 3^epped (by gate L45 being opened) in between, so that tea first -1 goes into one place in the answer and the next one goes into the sot pl?ce to tfc-* ri/*ht. 6,2,8. Ihe shift circuit
When an over-draft occurs gate E9 is opened. This passes a general oJ.se (GP) which goes through the inverter F9 and sets the N* and the S receivers,
ii O
These receivers cause the numerator to transmit on add and clear, and the shift accunulator to receive on a. The slow buffer output of the Sa receiver goes through the inverter L8 to three gates. One of these, gates, LI, passes a central program pulse which steps the numerator ring changing the sign in the sign indication circuits in preparation for the next add-subtract cycle. Another gate, L45, passes a 1» pulse (l'P), corning fron gate F6, which goes to the pulse standardizar L-J, 11 and thence to step the quotient place ring. The third gate, K7, passes a central program pulse which activates the S^ and the R»a receivers. These receivers cause tho number now in the shift accumulator to be transmitted and cleared and received by the numerator accumulator.
The slow buffer output of the N'a receiver goes through the inverter CIO tc open the gates C9 and Cll. C9 passes a general pulse (GP) to produce » P pulse which starts the next add or subtract cycle. Cll passes a general pulse to produce a root reset pulse which is essential to reset the D'y and the ♦1 or -1 receivers in the case ot square rooting. In the case of division this circuit is not used since division pulses are passed by the buffer C12 to pro-
VI - 20
duce a root reset pulse each addition time. 6,2.9, The interlock and clear circuits
These circuits consist of three flip-flops and associated gates and inverters. One flip-flop (H, J48) renenbers whether the interlock signal has arrived or not (the interlock signal is the output program pulse for the Ladt operation of the sequence of computations which goes on simultaneously with the root or division process). Another flip-flop (K, J 50) renenbers the fact that the division or root process is finished. These two flip-flops open gates J49 and H50 which pass a central program pulse serially setting the flip-flop G, F 50. The interlock flip-flop H, J 48 nay be by-passed in case the interlock switch is set at "NI". In this case the CPP passes gate K49 instead of gate J49. The pulse passed by H5O resets the flip-flop K, J 50.
The output of flip-flop G, F 50 opens gate 63 in the activated trans- ceiver and gate F49. A CPP passes gate F49 and the inverter E49 to provide the CI' pulse. Thus, CL1 is a positive pulse. In some places a negative pulse is needed for the clearing action so the CI' pulse goes through a buffer E48 to produce the CI pulse — a negative pulse.
The CI' pulse does the following:
(1) May pass gate L48 (depending upon the position of the correspond- ing interlock switch) to reset the interlock flip-flop H, J 48.
(2) Turns on the buffer A8 causing the program ring to clear back to stage A,
(3) Turns on the buffer F3 resetting the flip-flop E 4, 5.
(4) Turns on the buffer C13 producing a root reset pulse which
resets the D receiver (E. F 10) and the *1 and -1 receivers. V
VI - 21
The CI pulse does the following:
(1) Resets the flip-flop G, P 50.
(2) Resets the denominator flip-flop C 1, 2.
(3) Turns off the inverter K2 causing the numerator binary to be cleared.
6.2.10. The initial clear
The initial clear gate opens gates E50 and K48. E5O passes a CPP to the inverter E49 producing the CI' pulse (see above). The CL1 pulse not only passes buffer E48 to produce the CI pulse but also passes gate KL8 to reset the interlock flip-flop H, J 48. The action of the CI and Cl» pulses in this case is exactly as described in the section above,
6.3. NUMERICAL CIRCUITS
The numerical circuits comprise the quotient place ring and its associated gates, the LI, -1, *2, and -2 receivers, the pulse gates. All of these circuits are located on the lower right hand corner of the block diagram PX-10-3Ct. 6.3.1. The quotient-place ring
The quotient place ring causes the -1 or ^2 which go to make up the quotient or the square root to arrive in the proper decade of the quotient or denominator accumulator. Also this ring causes the division or root proeoss to be terminated when the proper number of places (as determined by the divide- root-place switch, see section 6.1.6.) in the answer have been computed. The -1 and +2 receivers, open combinations of gates which pass groups (of the 1, 2, 2», >*> or 9 pulses) of pulses which represent the numbers *1, -1, *2, or -2.
The static output of each stage of this ring goes directly to one gate
VI - 22
tube and through an inverter to another gate tube. Thus, most of the gates connected to the ring are ncrcclly open and thoss connected via the inverters are ncraOly close. The ring cUs- -.o stagn one (tube 29) « Then, normally (after L-dtialiy tlaaring) gate K43 >1H be open a^d all cf the gates B42 to Ii2 t\1"- "cj op « P3XCJ.C K«i-?. i>s tho ring steps through various positions, one cf th? q'ter &,3 ;o 7/3 is eltays open., and all except one of the gstes Bl£ to i£ >ts conducting
In -he fcllcwisg discussion assume that the quotient p'ace ring is at sere 1 -nd t"-::- f.sz: whero the receivers +1, -1, +2, and -2 ar? each t.ctivated vill be discussed in succession,
(1) +1 receiver is activated. This causes gate 146 to be open passing a one pulse (IP) through the inverter and buffer system KA5» J45» and %5. Of the gate tubas B to UV2 only KZ»2 is open. Thus the one pulse passes this gate to the inverter Khh and appears on the ninth channel of the output Ping.
(2) -1 receiver is activated. This causes gates B45» G to K46 to
be opened. Gate G46 passes the nine pulses (9P) through the buffer and inverter systen F^5, EU5, D/*5, and E45 to the gate tubes B to L U3. Since all these g'-te tubes except K43 are open nine pulses appear on all. channels except channel nine (including the Hi enamel). The gates H to K 46 pass the 2P, 2«Py -ind the 4P through the buffer and inverter system K45, JA5, and HL5 to the gate tubes B to L U2. Since only K42 is open this gives eight pulses on channel nine. The g^te B/,5 passes the l'P directly to the inverter BW» of channel one. Thus, before the l'P arrives the quotient has received the number M98999 99999.
VI - 23
gter the 1*P arrives the accumulator has received the zsxfeer
M99000 00000, kL<± represents the canter -01000 00000.
(3) *Z reoeiser is activated. The gats L^6 is open. This gate rasses the 2? to the buffer arid inverter S7sten and then to the gates B to L 42. GeU Li2 passes these puls-s into channel nine.
(4) -2 receiver is activated. Gates E4& and C to E 47 are open.
567 passes nine pcls=s Lsfc o the ?JL channel and through all the gates 5 to L 43 scept F_3. Sates H, J, ^nd LX? pass the lr, 2?, and the 4? to give seren poises through r-^te Ll2 into the ninth chancel, 546 passes the 1»? into the first c-.-.-el. Before th= lr? arriTes tins denominator accumulator receives
M97999 99999. if.er the 1'F arrives tfes zenjcdnatcr accaaclator has received
rccra ooooo,
which represents the manner -C200C C000C.
The cuntient nlace ring is stepped fcy & 1*1 passing g^t** F6 and L45* >-*-=. ?-_ i5 coen exeunt in period HI (the reund-eff period} and gate LL5 i* opened tcce each shift cjcle.
Tne —jotient claee rinr also o-erf-ras a second function. 2cppcs« ■ tie places s-itch is set at eight. Tben, *toes the gaotieat place ring relate* Sage seres 5 there ssaj he eigM Oirito in the orient; the gate Ml 1&& sexier the oulse sccrcs oirounts] *il- conduct timing toe im-erter u«C off aaS opening — .. - ., . . ^g mandiSag tfl this oc-sition of ts*
.^.^ . ._ .-^ (—^feeing possl&Ip 3-n ed^* tigut sj&aaisBft
=r sxore not] the neon shift cj-1* ****• *S tt£* tin. tte «*S»* of gate B m r^te 2c settls* ste owe **r« fUo-floc to, J|. *&£s «S» «■
VI - 24
eate F6 and thus the quotient place ring is stepped no farther, even though tte shift of the number in the numerator accumulator takes place. This means ttst the nunber which may be added or sub racted as a result of the round off procedure is put in this same place (that is, in channel three).
6X EXAMPLES
The fojlcr.a-ig table gives the setting of the program, control switches
in the different exarples:
Example 1 Example 2
Rinorator receiver switch a a
numerator clear switch C C
Denominator receive switch 0 0
Denominator clear switch C 0
Interlock switch I NI
Answer disposal switch 1 1
Round-off switch HO RO
Root-divide place switch D 8 R 10
6.Z».1. *■■ division example
Addition and
pulse tine Discussion
0.17 Program pulse arrives at buffers 67, 68, and 69.
The output of buffer 67 activates the D« receiver. The output of buffer 68 activates the NT receiver. The output of buffer 69 activates the transceiver in the divider. The output of the cathode follower 64 opens the sate A41. One of the buffers 61 gives a signal through the interlock switch to open the gate UB. The other buffer 61 £ives a signal through the root-divide and round- off switch to open gates K5 =Jid K6.
VI - 25
Addition and
jmlse time Discussion
1.1 Tfte numerator and denominator accumulators are receiving the
to numerator and denominator. (It is assumed that the program
1.10 pulse which activates the divider is used to cause the trans-
mission of the numerator and denominator from whatever units contain them,
1.17 A general pulse (gated CPP) passes gate K6 to provide the first
division pulse (DP). This DP passes gate A10 to step the program ring to stage B. The output of stage B opens gate D6» During this time the PLI static lines from the numerator and denominator to the sign indication circuits are setting up.
2.17 Another DP steps the ring to stage 1 causing gates B8, A7, and
B7 to open, A general pulse (GP) passes gate D6 which may or may not step the numerator ring and/or the denominator flip-flop depending upon the signs of the respective quantities.
3.17 A GP passes gate «7 clearing the program ring back to stage a.
A GP passes gate B7 setting the flip-flop A, B 6 closing the gates A10 and All. A DP is passed by gate B8 producing a first P pulse. This P pulse activates the K receiver and either the DA or the D§ receiver (depending upon the signs). Activating the N re- ceiver causes gate L10 to open. Say th?t the sitfis arc alike then the Ds receiver will be sot and thus gate Gil opened.
4.17 A DP passes gate L10 and activates the receiver Qy. This causes
gates Dll and D12 to be opened, a DP passes gate Gil setting the ♦1 receiver, a GP passes the buffer C5 and resets the % and the Dg receivers.
5.1 Gate LA6 passes a one pulse (IP) which passes gate KA2 to go
into the ninth decade of the quotient accumulator.
5.17 A DP passes the buffer C12 to reset the +1 receiver. The Q
receiver is reset by a CPP. assuming there has been no over- draft gate D9 passes a GP to produce the next P pulse. This P pulse sets the Na and the Dg receivers.
6.17 Same as 4.17.
7.17 Kssuming there has been an over-draft the gate E9 passes a GP
which sets the N. and the Sa receivers. This causes gates U5, K7, and LI to be*opened.
8.1 The numerator is being transmitted to the shift accumulator.
to
8.9
VI - 26
Edition and
pnlse time Discussion
S.10 A l'P passes gate F6, U5 and steps the quotient place ring
to stage 2. The numerator accumulator clears.
8.17 A CPP passes gate K7 activating the S and N receivers. The
activating of receiver Na opens the gate C9.a
9.17 A GP passes gate C9 to produce a P pulse. This starts an add
cycle (since the numerator ring has been stepped). That is, this P pulse activates the N and the D receiver. Activating the D^ receiver causes gate Hll to be opened.
10.17 As in 4.17 the Qy receiver is activated and a DP passes gate Hll to set the -1 receiver.
0.10 A l'P passes gates F6 and L45 to step the quotient ring to
stage 7. The N_ and S^ reoeivers are set. Gate A41 begins to conduct opening gate E6.
1.17 Gate C9 passes a GP to provide a P pulse which activates the
Na and the Dg receivers.
2.17 « DP pssses gate L10 setting the Qy receiver, h DP passes gate
Gil setting the +1 receiver, .assuming there has been an over- draft gate D12 begins to conduct opening gate B9»
3.17 A DP resets the -1 receivers. A GP passes gate E9 activating
the Sa and the N receivers. This pulse from E9 passes E6 to set the pulse source*' flip-flop E U, 5. Thus, this is the last addition time in which general pulses (GP) and therefore division pulses (DP) are produced, hs before the output of the Sa re- ceiver opens gates K7, L45» and LI.
4.10
Gate F6 is now closed so no l'P is passed,
4.17 CPP' s pass gates K7 and LI to set the S^ and the N receivers
and to step the numerator ring, respectively. * CPP passes gate F5 to produce the first HIP puis*. This HIP pulse goes through the buffer A12 to step the program ring t» stage B. It also passes gate K5 to produce a round-off pulse (ROP).
5.17 An ROP pulse (a HIP gated by K5) passes gate C8 to produce
a P pulse which activates the Na and D receivers, a HIP pulso passes the buffer A12 to step the program ring to stage 1,
VI - 27
pujje time Discussion
6.1 The denominator is added to the numerator.
to
6.9
6.17
A HIP pulse steps the program ring to stage 2. The N. and D receivers are not reset since there are no GP'a to pass the A buffer C5. *—
7,17 A IIIP steps the program ring to stage 3»
( 8.17 A IIIP steps the prograz^ring tfo stage 1^
9.17 A IIIP steps the program ring to stage 5. This opens the
gate D4.
10.1 The denominator is added to the numerator for the fifth time.
to Suppose that this does not produce an overdraft in wnich case
10,10 gate K12 remains open.
10,17 AnROP pulse passes gate D/» to reset the Ka and the Da receivers.
A IIIP steps the program ring to stage 6, opening gates E3 and J13.
11,17 AnROP pulse passes gate J13, K12 (assuming there was no over-
draft), and gates J8 and J10. The output of J10 sets the Qy receiver. The output of J8 is passed by gate F8 or G8 de- pending upon the signs and sets the +1 or the -1 receiver. A IIIP steps the program ring to stage 7. A CPP passes E3 to reset the pulse source flip-flop.
12.1 4-1 or -1 is added into one decade of the quotient accumulator.
to
12.10
12,17 A CPP passes F4 and K6 to produce a DP which resets the +1 or
the -1 receiver. A CPP passes L50 to set the flip-flop K, J 50.
(Wait for interlock pulse)
0.17 Interlock pulse (program output pulse of some ***"**) ^s
on one of the buffers F k^lS and Gtf settxng the flip-flop H, J UB.
VI - 28
Bse tlme- Discussion
1>17 A CPP passes J49 and H50 to set the flip-flop G F 50 and
(13.17)* reset K, J 50. Flip-flop G, F 50 JZS^£ 62 IJlkT
transceiver to open.
2.10 The carry-clear gate passes gates A48 and A49 and appears
[14.10) at terminals on the front panel.
2.17 A CPP passes F49 to produce the CI and Cl« pulses.
(14.17) The C.V pulse does the following
(1) passes gate L48 to reset H, J IS,
(2) passes buffer A8 to clear the programming
(3) passes buffer F3 to reset the pulse source flip-flop £ 4, 5.
(4) passes buffer C13 to reset the D receiver (E, FID, Fll, Ell, E12) and the *1 receivers. Y
The CI pulse does the following
(1) the flip-flop A, B 6 to reset.
(2) resets the denominator flip-flop C 1, 2.
(3) turns off the inverter K2 clearing the numerator binary ring.
A CPP passes gate 68 in the transceiver resetting it and
being transmitted,
A CPP parses D46 to activate on= of the answer disposal
transceivers.
6.4.2, A square root example
Addition and
pulse time Discussion
0.17 Program pulse arrives at buffers 67, 68, and 69.
The output of buffer 68 activated the N^ receiver, and the output of 69 activates the transceiver in the divider. The output of the cathode follower 64 opens the gate A43. One of the buffers 61 gives a signal through the interlock switch to open the gate K49. The other buffer 61 gives a signal through the root divide and round-off switch to open gates K3 and K4.
*Her.d this time if interlock signal arrives before completion of division process.
VI - 29
Edition and
pise tlae Discussion
U The radicand accumulator (same as numerator) is receiving
to the number to be square rooted.
1.17 A GP (A cpp Passes by gate F4) passes gate K3 to produce the
first square root pulse (SRP). This SRP passes gate All to step the program ring to stage B, opening gate D6.
2.17 Krtothor 3KP steps the program ring to stage 1 causing gates
A7, B7, KC , i-nd G7 to open. A GP passes D6 but has no effect on the denominator flip-flop sine;; the denominator contains the number +00000 00000 at this time. Tf the radicand were negative the binary ring mould be stepped.
3.17 An SRP pulse passes gates K8 and G7 setting the Dy and the *1
receivers., respectively.
A GP passes gate a7 clearing the program ring back to stage a, h GP passes ga*:e B7 sotting the flip-flop k, B 6 causing the gates AID a-:d .11 to close.
i.17 The outpu+ of the Dy receiver prsses gate Dll, opens gate D9
which allows e GP to be passed producing the first P pulse. This F pulse activates the N and the D receivers (since the denominator consists of *1 in a certain decade).
5.1 The +1 in the denominator is subtracted from the radicand.
to
5.10
5.17 A GP resets the IIa and the Ds receivers (from buffer C5).
An SRP passes gate L9 to set the Dy receiver and gate G12 to activate the +2 receiver.
6.1 »2 is added into the denominstor giving 3.
k CPP resets the D and the +2 receivers.
assuming there is no overdraft gate Dll is conducting and thus,
D9 passes a GP to produce the next P pulse.
An SRP activates the Dv and the *2 receivers.
assuming there is an over-draft this time gate D12 conducts
opening gate E9.
« GP passes gate E9 and sets the S and NA and Dy receivers, and it prssos g*te G9 to set the -I receiver.
VI - 30
Discussion
i*! J?d6d^? *?" *5 that "as in the dencninator accumulator, The radicand is transmitted to the shift accumulator. h»P steps the quotient ring.
A CPP passes K7 to activate the Sn and the N receivers and
passes gate LI to step the numerator ring.
-1 is again added to the *40 in the denominator accumulator giving +39.
The radicand is transmitted back (through a shifter) to the numerator accumulator.
a GP passes gate Cll to reset the D and the -1 receivers. A GP passes gate C9 to produce another P pulse.
A 1'P passes gates F6 and LA5 to step the quotient ring to stage 9, causing gate A43 to conduct and, thus, opening gate E6.
The S and Na receivers are set by a CPP through gate K7. The numerator binary is stepped to minus (a minus radicand)
A GP passes gate C9 to produce a P pulse. This pulse activates the % and the D receivers.
An SRP passes gates L9 and G12 to set the Dv and the +2 receivers, respectively. Assuming there has been an overdraft gate E9 opens.
* GP passes gate E9 activating the Sa and the NA receivers, and passes gate E6 to set the pulse source flip-flop Eh, 5. Thus, this is the Ust addition time in which GP pulse, and therefore, SRP pulse will be produced.
What happens during these addition times is exactly a repetition of what happens in the case of division (explained in example 1).
A CPP passes gates KV? and H50 (opened by the program ring being at stage 7) and sets the flip-flop G, F 50.
VI - 31
Edition and
gflsg tine Discussion
13.17 k CPP Passes gate FA9 producing CI and CI1 pulses.
The CI pulse resets the coincidence flip-flop G, F 50, and
clears the quotient ring and the numerator ring.
The CI' pulse clears the program ring, resets the pulse
source flip-flop (E 4, 5), and rssets the D and the +1 and -1
roceivers. y
The CI pulse resets the flip-flops a, B 6, and C 1, 2.
The output of the coincidence flip-flop causes the gate 62 in
the activated transceiver to conduct, which in turn opens the
gates BA8, one of the gates C46, DZ*6, D47, or EV7 (for answer
disposal), and gate 68 in the transceiver.
1A.10
The carry-clear gate passes gate BA8 and clears the numerator accumulator.
li,,17 A CPP passes gate 68 and is transmitted as an output program
pulse.
A CPP passes gate DA6 and activates the first answer disposal receiver.
VII -1
VII FTJHCTIOH TABLE
There are three- fraction tables in the ENIAC; each stores the values of a function for 1DU. values of the argument. Associated with each function table is a portable function table supporting an array of switches on whioh the operator can set the values of the function. For each value of the argument the portable tabls has twelve digit switches and two PM switches (thus, the portable table has 12l»8 digit switches and 206 PM switches).
Panel #2 (the right hand panel) contains eight master digit switches and two master PM switches. These are for setting any digits (as many as eight) that are the same for all values of the argument. The PM master switches can be used when all function values set up in the table are of the same sign, caking it unnecessary to set the PM switches of the table.
Thus j, altogether, for each value of the argument there are twenty digits (eight of which are the same for all arguments and twelve of which can vary from argument to argument) and two Pi5 signs (determined either by the caster PM switches or by the settings of the various PLI switches on the portable table). Tho two PM signs enable the operator to set up the values of two functions for each argument allotting the twelve variable digits and the eight master digits to the two functions in any manner. This allotting of digits to the two functions requires special adapters at the two function table outputs (see Section 11.6.5.).
Four of the master switches (Ax to A4) feed lines 7 to 10 of the A output. Master switches E^ to B^ feed channels 7 to 10 of the B output. The P-l master switch feeds the FM channel of the A output and PM£ master switch feeds the PM channel of output B. The left h^nd six columns of switches on the portable table feed channels 1 to 6 of the A output. The right hand six columns
VH
of switches feed; the lines one to six on the B output.
If one desires to transmit any other combination of these channels into one digit trunk then the appropriate adapter must be constructed (see Secticn 7-? *?«)*
The first:" on table transmits in five addition times the functional rsluc (or any of fcir neighboring functional values depending upon the setting of the argument switch— this is for interpolation purposes). By using the repeat sv.lt.:-' thci function table may transmit the functional wlue n times Q$n£?) in j:+v addition times.
7.0. IvTRODUCTIOH
In thn unper right hand corner cf the block diagram PX-7-304 appear the switches of the portable function table. In the upper left hand corner are the units and tens argument rings. Between these and the table switches are the table input gates or table selectors. Below the argument rings (left center of the diagram) is the program ring, and below this, two program con- trol circuits (there are nine other program control circuits) are illustrated. At the bottom center of the diagram are the pulse gates which pass combinations of the 1, 2, 2» , 4, and 9 pulses to make up pulse representations of the digits 0, 1; 2, ..., 9. To the right of this are the master switches (which are used to set up digits which do not change for all 104 values of the argument) and in the right hand corner are the transmitter circuits.
The table output gates and all circuits below them (on the diagram) including the pulse gates ere located on the right hand panel (panel #2) of the function table. The switches (in the upper right corner) are on the portable unit. All other circuits (including the rings, the flip-flops, and the program
VII - 3
control circuits) are located on the left hand panel (panel #1) of the function table.
There are three complete function tables. Each one is identical with the others so anything said in the following discussion applies to all three.
For purposes of discussion the circuits of the function table are divided into three types. The program control circuits comprise the eleven transceivers and their associated switches. The common programming circuits cnprise the program ring and its associated gates, the argument flip-flop, the subtract flip-flop, end the add flip-flop. The balance of the circuits make up the numerical circuits. The numerical circuits include the argument rings, the table input gates, the portable table, the table output gates, the pulse gates, the constant switches, FM master switches, delete switches, subtract pulse switches, and the output transmitters.
7.1. THE PROGRAM CONTROL CIRCUITS
7.1.1. The Transceivers
There are eleven transceivers located in the #1 panel of the function table. These are standard, that is, they are exactly the sane as those used in the accumulators and most other units of the ENIAC.
7.1.2. The Argument Reception Switch.
The buffer which feeds this switch (that is, the cathode follower in the transceiver) serves two functions, namely, to control the transmission of the argument and the stepping of the program ring. The argument reception witch has three possible settings controlling the reception of the argument fron some other unit of the ENIAC. On all three settings the fast buffer out-
vn - 4
put (tube 64) of a transceiver goes tc gates D4% E49, or F49, one of which passes central program pulses which step the program ring. If the switch Of the activated program control circuit is set on NC, a central program pulse passed by gate J48 (opened by stage -3 of the program ring so that J48 is open at the beginning of the program) will turn inverter H48 off, and pass gate K46. The pulse will then go through the transmitter J-L 46, and appear on the front panel (terminal labeled NC, see PX-7-302). From there it can be taken (via junpers and program trays) to some other unit of the ENIAC to program the argument transmission. If the switch were set at C the action would be «rfn^l*r except the output pulse would pass gate H47 and be transmitted from the trans- mitter J-L Ul, Supposedly, the NC circuit would be used when the argument is not to be cleared in the transmitting accumulator, and C is to be used when it is to be cleared.
These circuits are controlled by the fast buffer outputs (tubes 64 and 65) of the transceivers. Since these outputs have a small tine constant the input circuits to the gate tubes have extra capacity purposely added. This delays the opening of these gates; keeping them from opening in time to pass part of the same CPP which activated the transceiver. 7.1.3. The Program Switch,
Deck 1 of the program switch determines whether plus or minus the functional value is to be transmitted. When set on A (add), and a program control is activated, the output of tube 61 in the transceiver causes the inverter E48 to stop conducting, opening the gate E47. When the ring is in stage zero this gate passes a pulse which sets the add flip-flop (tubes C46, Ul). If the program switch is on S, then inverter E46 (the other triode) stops conducting, opening gate E46. Then, when the ring is on stage zero the subtract flip-flop
vn-5
D46, hi i» M*« Thc timing of these operations is illustrated in seetion 7.2.1.
Deck 2 of the program switch determines whether the functional tsiue itself or one of the four neighboring values is to be transmitted. If the reader will check the connections from the argument rings to the switches of the table he will note that the table number is exactly two less than the number registered in the argument rings. Thus, if x denotes the argument then normally the function table would transmit f(x-2). The number transmitted and the corresponding setting of the program switch is as follows:
Program switch setting Number transmitted Number in argument
rings
-2 f(x-2) x
-1 f(x-l) x*l
0 f(x) x*2
♦1 f(x+l) x*3
* +2 f(x+2) x+4
If the program switch is set at +1, for example, gates H44 and iUU nill be opened by the output of the buffer 61 of the transceiver. When the program ring is at stage -1 gate E42 will be opened and three pulses will pass HU and Ikk through the inverter ZUU and gate E42 and into the units argument ring. This changes the argument from x to x*3 and the function table will now transmit f (x*l) . Note that stage -1 of the program ring must open gate UZ in time to pass a IP. Since the gate is physically close to the ring there i. no difficulty in doing this with the usual two to one safety factor.
vn - 6
7,1.4, The Repeat Switch
This switch determines how many times the functional value is trans- nttted. If it is set at 3 (as illustrated) the functional value will be trans- mitted once when the ring is set at stage one, again at stage tvro, and the third tine at stage thr^e. The output of stage three (which is now positiaa) will go through +.crair.al three on the repeat switch and open gate 62 in the transceiver. This causes the inverter 65 to go off and opens gate 68 giving an output progran pu\se et the end of this addition tine. The output of the buffer 6> ■xr-i., -vf tie inverter D48 opening gates 'A/»3. S4£, and C4£. These pass centraj orc,?ram pulee^ (CPP) which clear all threo rr'-rg- and reset all three flip-flops.
Thus, tie functional table will transmit a functional value n times in n+k addition tur.es where n is any number between one and nine. Note that the accumulator which is to receive the function must be programmed to receive during either the whole n+4 addition times, or during the last n of the n*4« Consequently, if it is programed simultaneously with the function table, it can receive the function only 5 tines using a single transceiver. If, however, it can be programmed U addition tines later than the function table, the set- ting of its repeat switch can be the sane as that of the function table, and the function table can transmit to it the full 9 times.
7.2. THE COMMON PROGRAMMING CIRCUITS
7.2.1. The Program Ring
The program ring is a thirteen stage ring located on the left center of the block diagram. The following table illustrates what happens at each stage of the ring.
VII - 7 TABLE 7^2
Addition Ring Effect
Time Stage
0 -3
1 -3
Program pulse is received at a transceiver. At pulse time seventeen of this addition time the ring steps to stage -2, and, (depending upon the setting of the program switch), a pulse may be tf-ansndtted by «. 46 or J-L 47. Usually the pulse transmitted here will be used to program the argument transmission from some other unit of the EMIAC.
The buffer KA6 will go on turning the inverter 148 off, opening the gates D42 and H42; allowing the argument to be received.
Depending upon the setting of the program switch certain of the gates F44 to L44 may have been opened. Thus, from zero to four pulses are passing the inverter E44 and at this addition tine these pass the gate E42 and enter the units argument ring. Gate F47 is also opened, allowing a 1» pulse to set flip-flop B46-B47; this flip-flop, through buffer A46, turns off inverters Bl to LI and All, in turn permits one of the table input gates to conduct and energize one entry of table. The- output of the zero stage opens the gate G4S. At pulse tine seventeen of this addition time a central program pulse (CPP) passes this gate, turning off the invert or F48. Depending upon the setting of the program
I
TABLE 7-2 miartn VH - 8
switch, eithcf gate E*6, or 1*7 is open. Thus, the output of the inrerter W sets either the add or the subtract flip- flop causing either the function value or minus the functional value to be transmitted daring addition time 5 (and subsequent addition times for repeat switch settings above 1)„ 1 Certain of the pulse gates are opened during this addition time, and the functional value is transmitted ever the digit output (SX and ST in lower right hand corner). The output of stage 1 of the program ring connects to terminal 1 on all the repeat switches. 6 2 The functional value is transmitted a second time.
3 The functional value is transmitted for the third time, and (if the repeat switch is set on three as illustrated) gate 62 is opened in the transceiver. Then buffer 63 turns off inverter D48 opening gates A48, BUB, and C48, causing the rings to clear and the flip-flops to be reset.
7.2.2. The Argument Flip-Flop
The argument flip-flop B 46-47 is set by a V pulse passing gate F47. This gate is opened when the program ring is at stage -1. '-Then the flip- flop is set it turns on buffer kU7 which turns off the inverters Bl to LI and * U. This determines the time at which one of the table input gates conducts.
7.2.3. The Add and Subtract Flip-flops and the Pulse Gates
The following table gives a list of the gates opened and the effect *hen the add or the subtract flip-flop is set.
TABLE 7-?
VII - 9
|
Channel |
Add |
Subtract |
|
|||||||||
|
IP |
2P |
2'P |
4P |
9P |
Total . pulses |
IP |
2P |
2«P |
4P |
9P |
Total |
|
|
0 |
- |
- |
- |
- |
- |
0 |
- |
- |
. |
. |
L«4 |
9 |
|
1 |
K»4 |
- |
- |
- |
- |
1 |
- |
K'l |
K«2 |
K«3 |
- |
8 |
|
2 |
- |
- |
J»2 |
- |
- |
2 |
J*U |
J'l |
J' 3 |
- |
7 |
|
|
3 |
H«4 |
- |
H»2 |
- |
- |
3 |
- |
H'l |
- |
H'3 |
- |
6 |
|
4 |
- |
- |
- |
G'2 |
- |
4 |
G'4 |
- |
- |
G'3 |
- |
5 |
|
5 |
F«4 |
- |
- |
F'3 |
- |
5 |
- |
- |
- |
F»2 |
- |
4 |
|
6 |
- |
E»l |
-. |
E«3 |
- |
6 |
E'4 |
- |
E«2 |
- |
- |
3 |
|
7 |
D'4 |
D'l |
- |
D'3 |
- |
7 |
- |
- |
D«2 |
- |
- |
2 |
|
8 |
- |
C'l |
C'2 |
C'3 |
- |
8 |
C«4 |
- |
- |
- |
- |
1 |
|
9 |
- |
- 1 |
- |
- |
B«4 |
9 |
- |
- |
- |
- |
- |
0 |
The outputs of the pulse gates go to transmitting circuits, (ampli- fiers) (tubes B1 to L1, 5 to 10). The outputs of these transmitting circuits go to the various table output gates, the zero-nine channels go to the P and 1! terminals on the PM master switches, and through buffers B'63 to L'63 they all go to various terminals on the constant switches. 7.2.4. Use of the Function Table for Programming '.
The function table can be used to obtain program pulses on any of as Eany as L4 channels when a particular program control circuit is excited. The choice of output channel is controlled by any two digits of the number used as an argument, and registered in the argument accumulator.
vn - io
To accomplish this, an adapter must be used in back of the function Uble on the cycling unit trunk. This adapter (PX-4-U9) adds a central pro- gram pulse to the 9P lines of the function table panel #2.
Now, suppose that all the switches, on the portable table, for a particular argument are set to one; with the exception of one switch, which is set to "nine". Whenever the function table is programmed and the appropriate argunent is stored in the argument accumulator a CPP will be transmitted over the channel corresponding to the sw|tch which was set to "nine."
The nine pulse lines are used for this purpose since they also feed the PM switches. Consequently, the portable table can be used to give output pulses on any of fourteen channels (that is, twelve digit channels and two PM channels) . 7.2.5. Initial Clear
The initial clear gate opens gates kt& to CA8. The output of C/*8 resets the argument flip-flop (ft+6-47) and the add and subtract flip-flop (CA6-47 and D46-47). Gates klfi and B48 operate in parallel to turn off three inverters H9 to C^9. kU9 and B49 in parallel cause the argument rings to clear. C49 causes the program ring to clear.
If the buffer 63 in any transceiver conducts, (as it will at the end of an operation for which its program control was activated), the inverter DUB stops conducting, opening the gates kl£ to C/3 giving the same effect as the initial clear gate.
7.3. THE NUI/.ERICAL CIRCUITS
7.3.1. The Argument Rings
When the gates DW and H42 are opened (at stage -2 of the program
ring) the two digits of the argument arrive over channels five and six of the input terminal and going through the pulse standardiiers (J-L 42 and A41, B-C 42) step the units and tens rings to the proper position. When the program ring reaches stage -1, zero to four pulses may- be passed by one of the gates F44 te U4 through gate E42, to step the units ring the corresponding number of positions. If this causes the units ring to step through stage nine gate A42 will be opened to pass the carry over pulse. This pulse goes through the inverter and buffer G42 and steps the tens ring one place. Note that the tens ring has eleven stages; also there is never any delayed carry-over problem. The argument will- never exceed nine in the tens place but the carry over may give ten, thus, the
extra stage.
v
Consider the control of the table selectors by the rings. After clearing (as illustrated) the rings each set at stage zero. This causes the inverters K2 and K26 to be non-conducting. Suppose that a program control is activated, and the argument In tf», Then when the argument flip-flop is set the inverter LI conducts raising the potential of both grids of the table in- put gate (or table selector) K12. Incidentally, one control grid of several other table input gates will swing positively at this time, (for example, gates K13, K25, and Kll, and others not illustrated), but since the other grid remains below cut-off, (because other inverters associated with the tens ring remain on), the tubes do not conduct. A similar statement is true for the gates A to K 12.
Thus, when the program ring is at stage -1, one of the table input gates begins to conduct and one of the horizontal buses of the portable table has a negative swing of potential.
The action of those inverters and gates is explained in some detail
in section 1.2.3.)
VII - 12
7.3.2. The Table Input Gates
There are IC4 table input gates corresponding to the argument values tf-2, -1, 0, 1. 2, B.„, 100, and 101. This gives B ra^n of ^g^r, values ' of 0.. 1, ..... ?'v -*Lth the extra values on each nnd for plirp. sec o* i .tcrpolatim. Of the las control -aics of aach gate tube, one connects to tiu catput of an nwerter controls 3 by th- proper stage of the units rinr, sfrf ths ether control grid connects to the outputs of two inverters; one cj.-trf.ii.-dh7 the tens ring, and the othej by th; a-gurvnt flip-flop. In order for any par-rcuTar gate tube to conduct all three inverters must bo non-conducting. Thus, even t.;ouj-h the irgunent arrives in the rings earlier, none of the table input g^tts conduct until the argument flip-fl&p is set at stage -1 of the program ring, Note that this flip-flop is sot by a one primed pulse (l'P). The timing here is illus- trated by table 7-4,
table 7-4
Addition I Pils- Tiao J_Ti^e_
_0
1
1 -:
+-~
17
1 to 10
17
Activity
t*ro;^rzijping pulse- arrives at tlic function tally ~rtf~.r~:i transmission is pz Ojjranaed a-u receiving gates (Fly', %2) arc opened,
I-r^ran ring steps to stage -I oparrfig ,nites EL2 and F47.
i.:/.i,-.r'-" I adjustment takes place by C, \, 2, 3, or U pulses peeing gate E42.
Argument flip-flop is set by l'P.
Program ring steps to sta^e 0 oponinr; gate G48.
"Program ring steps to stage 1 op-ning gate 62 in the trans- ceiver (provided the repeat switch is at one) and a central program pulse passes gate G48 to set the add or the sub- tract flip-flop
"Functional value is transmitted.
Centra program pulse passes gate 68 in the transceiver to be transmitted and to reset flip-flop. CPP also pa sses »*tos ,.A3, B48, and OB to clear rin^s and reset flip-flops
VII - 13
7.3.3. %he Portable Table
The portable taole is a switching^network built as a separate unit, and connects to the function table unit through two IBI type plugs. Since the portable table is on wheels, the operator may quickly interchange it with one connected to any other function table.
Each portable tUsle mounts 208 ffi (sign) indication switches (two for each argument value) and 1248 digit switches (12 for each argument value). There are 104 PU switches and 624 digit switches on each side of the portable table.
7.3.4. Table Output Gates
The nine terminal on each of the 104 switches in the sixth column of the portable table connects to the inverter B'll. The output of this inverter goes to the gate B'12, which when opened will pass either nine or zero (no) pulses depending on whether the associated program control is on add, or sub- tract program respectively.
The ten positions of the switches in each column go to ten inverters. Each output from the ten inverters goes to one grid of ten gates, the other grids being fed by the pulse gates.
Thus, if horizontal bus 11 is energized and the sixth column digit switch is at 7 (as illustrated) the inverter D'll will cease conducting and the gate D' 12 will open. This gate will then pass 7 or 2 pulses depending upon the setting of the argument switch of the associated program control cir- cuit.
There are 120 inverters and 120 output gates on the digit channels. The two PH channels feed four more inverters and gates (C» to K» 61).
The outputs of the digit gates (l?b.led *5 to ,10, and B5 to BIO) go through inverters and buffers to transmitters, (these transmitters use a
vn - u
6L6 in place of the usual 6V6) and then to terminals SX and ST. The outputs of the FM gates go to the FM master switches (Fl^ and FM2 associated with the A and the B outputs respectively). 7.3.5. The FM Master Switches
The FM master switches make it possible to determine the sign for all the table entries at once instead of setting the individual FM switches on the portable function tables. This is useful only if all entries are- of the same sign.
There is a FM master switch associated with each output (SI and ST).
These switches determine the sign indication transmitted on the channel of the
respective outputs. Each switch has three settings, Table, P, and H* The
following table gives results of various settings of these switches.
Master switch Pulses transmitted over the FM channel
setting Add flip-flop set Subtract flip-flop set
P 0 9
M 9 0
Table 0 or 9 depending upon the setting of the corres-
ponding FM switch on the portable table.
7.3.6 The constant switches and the delete switches
There are eight constant switches, four associated with each of the outputs SX and ST. If the first few digits of a function are the same for all arguments used, these switches simplify the procedure for setting up the values of the function. Therefore, when some program control is activated the numbers set on these constant switches (or complements) will be transited over the corresponding channels regardless of tKe value of the argument.
The outputs of the transmitters associated with the pulse gates comes through buffers B'63 to L'63 to ten of the positions on each of these
VII - 15
switches. Two other terminals on each of these switches make available the outputs of the two PM master switches here. This is ' to help provide the proper complements.
The delete switches are provided on each of these channels in case the operator desires to transmit nothing on one or more channels.
7.3.7. The Subtract Pulss Switches
Since the complementation provided by the add or subtract flip-flops and pulse gates gives complements with respect to ID11 <-l, it is necessary to provide a correction pulse to get complements idth respect to 10°. The correct pulse switches enable the operator to provide this correction pulso in any of six channels on each output, namely, A5 to A10 and B5 to BIO.
The output of the subtract flip-flop goes through the inverter D45 to the gates A«64, The 1»P is passed by these gates through the inverter A' 63 to the buffers A«6l, A»62 to L«62.
These subtract pulse switches enable the operator to divide the 12
variable digits set up on the portable table into arbitrary groups and cause
n each group to give complements with respect to 10 .
7.3.8. The output transmitters
The outputs of the constant switches go through the delete switches directly to transmitters. The outputs of the table output gates go through an inverter and a buffer to transmitters. Special adapters can be easily built to rearrange the outputs and allow transmission onto a single digit trunk.
If the operator desires, for example, to set up a ten digit function on the table and his function is such that the constant switches cannot be used then six of the digits can bo obtained from channels A5 to A10. The other four must come from four of the channels B5 to BIO and a special adapter must
VII - 1£
be used to get these ton digits onto one digit trunk. 7,3.9, Adapters
In designing an adapter for use on the function table outputs there arc two points to watch. First, the function table outputs (which arc to be used) are connected in a one-to-one manner to terminals corresponding to the trunk lines to be used. Secondly, if negative numbers are to be transmitted, then 017 unused lines, corresponding to accumulator decades between the HI unit and the first decade used, must carry 9 pulses in order to give the proper complements , This second objective can be accomplished by connecting the out- puts of some of the master digit switches (A, to A, or B, to B ) to the corres- ponding lines. The FH^ and PH2 positions of the master switches provides 9 pulses t the propor times.
If for any reason the master digit switches cannot be used for this purpose the adapter can bo made to transmit the number onto the trunk using only channels adjacent to the PM line (line 11). In this case a shifter can be used on the input to the accumulator. The shifter provides for the extra "nines" needed for complementing purposes (see section 11.3.)
vni - 1
VIII. THE CONSTANT TRANSMITTER AND IQd READER
The constant transmitter stores eighty digits on relays and twenty digits on constant set switches. Provision is made for twenty HI signs, sixteen associated with the numbers stored on relays and four associated with the numbers set on the switches. One of these PM signs is associated with each five digits. Thus, the constant transmitter can store twenty five-digit numbers and their proper signs. Provision is made to associate certain groups in pairs to form ten digit numbers. In one addition time the constant transmitter can transmit to some ether unit of the ENIAC any group of five or certain groups of ten digits and the associated sign.
Whenever it is desired to set up new constants on the relays in the constant transmitter, the T^* reader must be programmed to read a new card. This does not change the digits set on the constant set switches; these have to be changed manually.
The reader completely reads a card and stores the information on relays in the constant transmitter in 0.48 seconds. After about 0.3 seconds the start- ing circuits of the IEU reader are reset and will be able to remember a second signal to read (generally this fact is insignificant since computations cannot be started until the initial data is read into the constant transmitter and, also, there is no program output from the reader to start any computation until the end of the reading cycle). If in some manner it is arranged to program the next reading of a card before the first cycle is completed (this must not occur before say 0.4 seconds after the initial read program and this only allows a m safety factor) then, due to the clutch not dropping out, the reader will read a card in 0.36 seconds.
vni
Thus, the reader can read normally as many as 125 cards per minute not allowing for any computations in between. On the other hand, since each IBJ tine unit corresponds to about 1?0 addition times, and there is an interval cf about 1.2 units between the finish pulse and the dropping of the holding cam contact, it seems that even though the output of the reader is used to re- prograa the reader thai this same pulse can be used to cause transmissions from the constant transmitter safely (safety factor « 2:1). During the period of 100 addition times after this pulse, numbers could be transmitted from the con- stant transmitter, By the device mentioned above the speed of reading can be increased to as much as 160 cards per minute.
The description given here will be in terms of the following diagrams: 1) Constant Transmitter Cross Section PX-11-116, 2) Constant Transmitter Block Diagram PX-11-307, 3) Constant Transmitter and Reader Cross section, and 4) IBM Reader Diagram PX-11-119. The discussion will be divided up into the. following sections: 1) Constant transmitter program controls, 2) IBM reader program controls, 3) Numerical circuits of the constant transmitter, k) 131 reader, and 5) Examples".
.-8.1. CONSTANT TRANSMITTER PROGRAM CONTROLS
I
\ 8.1.1. The groups of numbers
As indicated above the constant transmitter stores twenty five-digit numbers and as many as twenty Bl signs. These are divided into five-digit groups called AL, AR, BL, %, ..., HL, HR, JL, JR, KL, and KR. The first six- teen groups AL to % are read from IBM cards vhile the last four groups JL to \ are sot on the constant set switches.
vni - 3
B.l.2. Transceivers
There are thirty transceivers in the constant transmitter. These are associated in groups of six. The first six transceivers control the first four five digit groups of numbers ^ to B^ The next six control the groups CL to ifo, et cetera. Finally, the last six transceivers control the groups JL to ftp which can- be set on the constant set switches (see panel two of constant transmitter, PX-11-303).
Two transceivers of a gr*»up of six are illustrated on FI-11-307. These arc for programs numbered one to six and control the first four five-digit grrups of numbers. The output from the cathode follower (tube 64, see PX-5-30) of each transceiver connects to two decks of the associated constant selector switch. The cathode follower is used to drive the svdtch because fast operation *f the circuit is required to m^Jce possible transmission of a constant during the addition time following the addition time in which the program pulse is received. The other outputs of the transceiver are unused. 6.1.3. The Program Control Circuits
Associated with the relays of groups one to four (likewise for five to eight, nine to twelve, snd thirteen to sixteen) there are eighty-eight gate tubes. In each group there are four gate tubes for each of the five digits (as the 1, 2, 2« , and U coded system is used to form the digits) and two gates associated with the F5i indication. There are six constant selector switches associated with each such set of 88 gate tubes (switches one to six with groups one to four, for example). The output terminals of these switches go directly to the grids of the gate tubes.
Switches 25 to 30 -re associated with the g»tes controlled by the constant set switches on panel two of the constant transmitter. There are only
vni - 4
$ gates associated with these switches since the gates associated with the correction pulse rje omitted. (This means that the operator sets up complements here as complement." .dth respect to 1011 and not 10n-2j,
Whenever a program pulse is received on the input terminal of a progr?m control, i.t li say, the output of the cathode follower (lube 64 in the transcei\er pl>ig-lr. urit* jces to the two decks of the const'jit selector switch. The results of the various settings on this switch are given in thl following table,
TABLE 8-1
Result Deck 3 Deck 2
Constant Selector Switch
Al The csthc3« follower potential The cathode follower potential opens
opens the )\. gat^s V>1 and A' 21, the digit gates for group 1, that is
gates B* tc L», 1 and 21.
AR Gate A' 41 'FM) is opened.
^m The m. pate A'l is opened.
Bl The Ftl gates A»2 and A«22
are opened
\ The FM gate k' LZ is opened.
Blr The FA gate /.' 2 is opened.
The ?H gate A«62 and digit gates
B1 to L', 41 and 61 are opened.
(A' 61 controls the correction pulse).
The m gate A' 62 and the digit gates B« to V 1, 21, 41, and 61 are opened,
The digit gates B- to L1 2 and 22 are opened.
The FA gate A' 63 and the digit gates B' to L1 42 and 62 are opened.
The HI gate Al 63 and the digit gates B' to V 2, 22, 42, and 62 are all opened.
Since the constant selector switches are connected in parallel, within any group of the same alphabetical letter "back circuits" would be created
VIII - 5
should one switch be turned to L or R when another is turned to UL. For example, in the first group of six constant selector switches, if one is set at ^ ?° rther can be set at AL or i^ without transmitting superfluous digits (in the case of a positive number), or the extraneous transmission of 9P and 1«P over certain channels (negative number). This means that if the number stored on groups one and two relays is transmitted as a ten digit number, then at no other place in the computation can it be considered two five-digit numbers, or vice versa.
If an activated program control has its switch set te A , the five digits of group one will be transmitted on channels 6 to 10. If the number is negative nine pulses will be transmitted over the PU channel (A'l turns tff the inverter A' 11 opening the gate LA3) and the correction pulse will be transmitted over channel 6 (A' 21 turns off the inverter it'll opening the gate EA5). In this case nothing is transmitted over channels one to five.
If an activated program control has its switch set at A^ the five digits of group 2 will be transmitted over channels one to five. If this minber is negative nine pulses will be transmitted over channels six to ten and over the PU channel (A* U turns off the inverter n»5l opening the gates F to K hi and LA4) and the correction pulse will be transmitted over channel one (At 62 turns off the inverter «»61 opening the gate AA5). The nine pulses transmitted over channels six to ten give the complement with respect to 10 and make it unnecessary to use a shifter in the digit transmission line.
If an activated program contrel has its constant selector switch set at A; the ten digits of groups one and two will be transmitted over channels «ne to ten. If the number is negative nine pulses will be trans- ited over the PM channel (AM turns off the inverter A«51 opening the gate
vm -6
u3) and the correction pulse will be transmitted over channel one (At62 turns off the inverter A' 61 opening the gate AA5)%
The groups one to sixteen (or AL to H£) behave in a manner similar to above. The gates associated with the constant set switches (J to K ) behave similarly except for the correction pulse (as explained above, or see Section ff.J.Z.). ij2. Reader Program Controls
The reader program controls are located in the initiating unit (see PX-9-3C7) . The ISI reader can be caused to read a card, (provided certain conditions are fulfilled in the reader), either by a program signal arriving at teminal Ri on the front panel (PX-9-302) or by pushing the reader start button on that panel.
8.2.1. Starting
If the reader start button is pushed the resulting pulse goes through the special pulse standardizer (61 and 62, reader start unit, see PX-11-307). The output of the special pulse standardizer turns off the inverters 63 causing the buffer 72 (PX-9-104) to go on. This sets the flip-flops (65, 66) and(67, 68). The driving tube 64 goes on closing the starting relay (located in the constant transmitter (Panel #3). If a program pulse is used to start the reader it comes in over Ri turning on the buffer 67 and setting the flip-flop (65, 66), but not the flip-flop (67, 68).
8.2.2. Resetting
After the reader starts to read the card a signal (a gate voltage) cones back over connection 129 (see PX-11-307) from the reader causing the flip-flop 65 and 66 to reset. This signal occurs early in the card reading cycle (when the minus indication is being read-before the digits are read
vm - 7
(see the cam time-table on PX-11-120). After this reset signal has. arrived any subsequent program pulse arriving over ^ sets the flip-flop and closes the starting relay. This causes the reader to continue and read the second card before stopping. The reset signal arrives from 800 to 1200 addition times after the print program signal. 8.2.3. The Finish Signal
Just as the IBM reader finishes reading the card a signal is sent over connection 127 to the special pulse standardizer (65, 66) causing the flip-fl«p 70 and 71 to be set . This opens the gate 69 and if the flip-flop 67 and 68 is then set the inverter 61 (Px-9-106) will go off opening the gate 62. The CPP passed here sets the flip-flop 63 in6 64 opening gate 68. This passes a CPP which goes through the transmitter (65-67) to the reader program output RQ. This same pulse goes through the inverter and buffer 69 and resets all three flip-flops.
The flip-flop 63 and 64 is a synchronized flip-flop, that is, it is set by a CPP gated by 62. The flip-flop 70 and 71 is not synchronized since it is set by a signal from the IBM reader. Thus, the gate 62 may be opened in such a way that it will pass only part of a CPP. If it fails to set the flip- flop 63 and 64 no harm is done since the next CPP will also be passed by 62 and "ill set the flip-flop 63 and 64. This flip-flop being set by a CPP will open the gate 68 in ample time for the next CPP. This arrangement insures that a standard synchronized program pulse is transmitted out or Rq. 8.2.4. Interlock
Since the process of reading a card takes a very large number of Edition times it is desirable to be carrying on pert of the computation while this is being done. There will be a place in the sequence of computations
vni -e
.here the numbers in the constant transmitter are used for the last time. Afc
this addition time the reader may be programmed to read the. next card. Since,
generally, it will not be known which process, that of reading the next card
or that of completing the rest of the sequence of computation, will be finished
first, an interlock feature is provided. The final output program pulse of the
sequence of computation is plugged to R . Thus, flip-flop 67 and 68 is set at the
end of the sequence of computations while flip-flop 70 and 71 is set when the
reader is finished. Only when both of these things have happened will the gate
69 conduct and open the gate 62, finally giving a program pulse out of R .
The reader start button through buffer 64 also sets the interlock
flip-flop (67 and 63). Therefore, -.<hen the reader start button is pushed
the reader reads a card and a reader program output pulse is obtained at R
o
at the proper time.
The initial clear gate causes all of these flip-flops to be reset. Rote that when the ENTAC is turned on the starting flip-flop (65 and 66) may come on in the set position and before a CPP arrives to reset it the reader may read one card.
8.3. NUMERICAL CIRCUITS Of THE CONSTANT TRANSMITTER
The niLicrirc.1 circuits of the constant transmitter comprise the sateen zroups of storage relays and their associated gates (A1 to L« 1 to 10, et cetera) the ~on.>tant and PM set switches (on panel 2) and their associated Pes, the in/ertcrs (A' to V 11, et cetera) and the pulse gates (A to K U to «, A, E to K IM L 43 and ftfc), and the inverters, buffers and transmitters U to L 46 to 50) ,
vni
S.3.I. The Storage Relays and their Gat.ea
This description of the storage relays „iU be given in tern* of the constant transmitter cross section drawing PX-11-116. On that drawing there appears a wiring diagram of group one relays, s schematic diagram of group one relays, a coding cam time table, and a cross section of the electronic circuits.
As the IBM card goes through the reader the positions on the card pass under the reading brushes in the following order (see the cam time table 71-11-120 or the small table on PX-11-116).
12, 11, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, There are eighty columns on the card and all of these pass under the reading brushes at once. Punches in the^ position will be used to indicate minus signs, while punches in, say, position four represent the digit four in that column.
To simplify the following discussion it will be assumed that leads nuabered one to eighty of the Reader connections go directly to the corresponding reading brush. Actually, these eighty connections may be made in any desired Banner simply by rewiring the plug-board on the Reader, see PX-11-305.
The relay labeled R,„ (schematic diagram of group one relays, PX-11-116) is a PU isolating relay which handles the first three groups UL, Ap, and B^. Referring to PX-11-120 it is seen that cam CB9 makes con- tact during the reading of the eleven position on the card. If there happens to be an 11 or 12 punch in whatever column the minus indication for group one is Placed, say column one, a circuit will be made through connection 97, intact Rab, and the piek-up coils of relays P^ and BI^ When these relays N Picked up they are held by a contact on W2. This holding is controlled
VIII -10
^connection 81 (for group one) and lasts at least (it may last longer, see Section 8.4.5.) until the next card has begun to be read.
The following table gives the various combinations of coding relays that are closed during the various positions of the card reading.
TABLE 8-2
|
Card position |
12 |
>11 |
0 |
i |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
|
Kith no minus indication |
ci |
C3 |
C3 |
C7 |
cl C7 |
C3 C7 |
cl C3 C7 |
c3 C5 C7 |
h C3 C5 IC7 |
|||
|
Kith minus indication |
i |
Cl C3 C5 C7 |
c3 C5 °7 |
=1 c3 °7 |
c3 C7 |
Cl C7 |
C7 |
Cl C3 |
c3 |
Cl |
The reader can check this table in the following manner. If the number is positive the coding relays Cx to Cg are connected in pairs to the coding cams CB2, CB4, CB6, and CB8. The coding cam time table shows that as position seven of the card, for example, is under the reading brushes coding cans CB2, CB4, and CBS are making contact. If seven was punched in the first column storage relays 1-A, 1-B, and 1-D will be activated through the contacts on coding relays Cy Cy and C?. Contacts on the storage relays will cause gate
VIII - 11
tubes L'l, K'l, and K'21 to be opened ultimately causing the 1, 2, and U pulses (^together seven pulses) to be transmitted over channel ten. If there had been a sdnas indication punch the HI relays (H^ and H^) would be closed (and held by the circuit through connection 81) and the coding relays would be connected to coding cams CHL, CB3, CB5, and CB7. If again, seven were punched In the first colunn, only cam CB3 is making contact when the seven passes wider the reading tnishes and the contact on C^ causes storage relay 1-B to be picked up. Ultimately, this causes the two pulses (complement of seven) to be transmitted over the tenth channel. Since the HI relays are closed, a contact on HC, causes gates A'l and i'21 to be opened. These gates provide (for a five digit number) for the minus indication (nine pulses on the FM channel) and for the correction pulse (to give eonplements with respect to 10 ). 8.3.2. The Constant and HI Set Switches
PX-11-307 shows that these switches connect directly to the gates for the numbers JL to Kjj. Only the switches for the first and tenth digits are dram out in detail for th2 groups J and K. There are four Hi switches, so these twenty digits can be used in groups of five and the signs of any one group set independent of the others. If they are to be used for ten digit numbers then both HI switches (JL and «^, for example) must be set to P or to 1J depending "pon the number.
The constant set switches sonsist of four part, mounted on two decks. The moving portion makes contact in such a manner as to open the 1, 2, 2' , and k gates in various combinations corresponding to the digit to which the switch N set. The gates opened by various switch settings is indicated by the crosses in the following table.
VIII -12
TABLE 8-3a
|
Gates |
0 |
Switch .^ttlnr |
||||||||
|
1 |
2 |
3 |
A |
5 |
0 |
7 |
R |
9 |
||
|
1 |
X |
X |
X |
X |
I |
|||||
|
2 |
X |
X |
X |
X |
X |
X |
||||
|
2« |
X |
X |
||||||||
|
L |
X |
X |
X |
X |
X |
.X |
In the case of negative numbers read from, cards the coding relays automatically take the complements with respect to 10 -1. This is not true of the constant set switches for groups JL to KR, that is, in setting up a negative nunber on these switches the operator must take the complement himself. No
correction pulse is provided by these PM switches so negative numbers are eet
n
up as complements with respect to 10 . The following table illustrates various
s*itch settings.
TABLE 8-3b
|
I.'unber to be set up |
Hi Settings |
Switch Setting! i |
||||||||||
|
JL |
h |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
|
|
♦23456 on JL and ♦78901 on J^ |
P |
P |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
0 |
1 |
|
-12345 on JT and L ♦78901 on Jg |
11 |
P |
8 |
7 |
6 |
5 |
5 |
7 |
8 |
9 |
0 |
1 |
|
12345 on JL and -78901 on JR |
P |
M |
1 |
2 |
3 |
U |
5 |
2 |
1 |
0 |
9 |
9 |
|
^345 67890 °nJIA |
P |
P |
1 |
2 |
3 |
U |
5 |
6 |
7 |
8 |
9 |
0 |
|
-^345 67890 °nJLR |
M |
P |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
1 |
0 |
vni-i3
u, THE IBl READffi
The IBI Reader will be described in terms of the wiring diagram B-U-119. At tne tup of this drawing are tables which give the locations of the reliys and cane. Note that the various parts of one ;-elay (for example, the hold coil, pirk-"p "oil, and various contacts) nay ba located in widely different places on iris dvawing. The tables at the top locate all of these parts. The terminal posts are located in the panel behind the motor generator. The connections to fie IBI plug (which plugs into a socket on the constant transmitter panel number three) are pictured in the upper right corner of the drawing, 8,4.1. The a-c Circuits
The Reader receives its a-c power by a standard 110 volt plug which plugs into a socket on the bottom of panel three of the constant transmitter. Power is furnished to this plug only when the ENIAC is turned on, plugs at the bottom or other panels, except printer panel #2, have power on them all the time. The a-c power goes through a switch located on the Reader to the motor- generator and through contacts (on H. D. relay at 1A) on a relay (pick-up coil at 2B) to the drive motor. Thus, when the power comes on the motor generator starts up. VJhen it reaches speed the 40 volts d-c cause the green light (on the front of the Reader) to come on and the H. D. relay to close starting the drive motor. The H. D. relay prevents the drive motor from operating in case of failure of the motor generator. U.2. Starting circuits
When cards are initially placed in the magazine, the magazine card lever contact (Mag. at CLC at 2B) is closed. This causes Relay R-l to pick-up. I this time neither the auxiliary read switch nor the ENIAC startinfe relay
viii -u
(in the constant tranBmitter, see PX-11-307) can cause the reader to operate since Relay 2 is not activated.
If in this case, the initial start key is pushed, the reader will ^erate, (assuming card stacker switch closed, that is, there are not too many r-rds in the card stacker) and feed a card into position before continuous roll II (ttet is, in position ready to be read by the control #1 reading brushes). Sha the card is in position here, relay R-2 is activated by card lever contact fl. Be* either the auxiliary read switch or the ENIAC starting relay can cause s card to be read. The initial start switch, since relays R-l and R-2 are each activated, cannot cause a card to be read at this point. Thus, upon closing either the auxiliary read switch, or the ENIAC starting relay the card passes under the #1 (control) reading brushes and stops in position before the #2 read brushes.
If any of the control arrangements (like plugging to control hubs on the plug-board) are being used the "control"* Instructions are now remembered by certain relays in the Reader. Note, that this memory depends upon the W) volt output of the notor-generator on the reader.
rith the first card in position before the #2 read brushes, a card lever contact (CLC #1) causes R-60 to be activated. If the auxiliary read switch is again operated this card will be read by the #2 read brushes and the (signed) numbers stored in the constant transmitter relays.
In practice the relay timing is such th* in initially placing cards in the reader (by placing cards in the magazine and depressing the initial start fcy)the reader may feed cards up to position before the £2 read brushes by run- ning th™* two cycles. In this case it is ready to imediately re^d the first IN. If the first card was fed only into position before the #1 or control
vni -is
b^bes (one cycle) no harm is done, if the reader is now programmed to read, relay H-60 being open, it will read the 1st card by the control brushea **»! reset or finish signal will be given out. Then, the starting relay still being closed, the reader will Mediately start another cycle in which the first card passes under the #2 brushes. When the cards are in position, relays #1 and fl are activated by the card contact levers, (Magazine CLC., CR. #1, CR. #2) ^ the start key becomes ineffective. After relays #1 and #2 are activated, contacts on them (at 3B) enable the auxiliary start key to cause a card to be read. A starting relay located in the constant transmitter (see PX-11-30?) has & contact connected in parallel with this auxiliary start key, A unit located in the initiating device (described in 8.2.) causes this starting relay to close asd thus causes the reader to read a card. 8X3. Kuaerlcal Circuits
There are two sets of 80 reading brushes, the first (§1) are the control brushes and the second (#2) are the ones which read the numbers and tfceir signs. The number two reading brushes (at 6B) read the numbers and W signs on the cards and via connections on the plug board carry the corres- ponding signals to the storage relays in the following ways:
(1) Directly to the storage relays (hubs located at 6D).
(2) For a column in which the HI punch occurs the connection is from the reading brush hub to one of the HI hubs (labeled "minus control" on the plug-board) (at 6D on PX-11-119) and from the other HI hub to the corresponding storage relay hub.
(3) Or, if desired, the connections from the reading brushes to the storage relays may be by way of the group selector relay contacts (at 6B and 6C). In this manner certain control punches may cause information from one set of reading brushes to go to either
VIII - 16
jie of two sets of storage relays, or such control punches may cause one set of storage relays to receive information from one of two sets of reading brushes [see Sections 8.4.4. and 8.4.5.) g.ii.4. Group Selection
There are sixteen five-pole, double-throw relay switches (relays R24 to R55, two relays to each switch, hold coils at 4C and 5C, contacts at 66 and 6C). The coils at 4C and 5C serve for picking up and for holding. These five- pole, double-throw switches may be used to rearrange the information coming Mo the storage relays. These relays are picked up by contacts on relays 7 to 22 (at 4C and 5C) in series with the cam P6. Once they are picked up they are held by cam P7,
Referring to the can time table ( PX-11-12G) we see that relays 7 to 22 cay be picked up any place in the card cycle, that is, from any punch (since can P5 makes contact all this time). If any of these relays have picked up, can P6 will cause the corresponding relays 24 to 55 to pickup at the end of the card cycle. Once they are picked up cam P7 holds them until the end of the next card cycle. Since the card going under the control brushes will go under #2 read brushes exactly one card cycle later, this means that a group selection control punch will activate the group selection relays during the time the card is passing under the #2 read brushes. 8.1.5. Reset Control and Reset Shunt
The storage holding relays (contacts at 7B, pick up coils at 3C) 4, 5. »d 6 cause the relays in the constant transmitter to hold their information. The time table shows that cam CB10 causes these relays to hold from position 12 on one card until 13.7 on the naxt card. That is, the information read I* one card is normally dropped out at the beginning of the reading of the next card.
VHI - )7
By plugging from the reset control hubs to the reset shunt the corresponding constant transmitter relays can be caused to hold their informa- tion until such time as the relays 56 to 58 are activated.
By proper plugging on the plug board connection can be made from the & read brushes through the pick up coU of relay 2J tc the digit selector. ten relcy 23 is activated relays 56 to 58 will be picked up by cam P8 at 8,5 in the eard cycle. A contact on relay 57 and cam PI causes relay 59 to pick up st 9.5 in the card cycle. This is shown on P -11-308.
Suppose that reset control is operated from a "three" punch in some column in what will be called a master card. Cards without this "three" punch (in that same column) will be called detail cards.
At the end of a cycle in which such a master card passed under the control (#1) brushes relays 23, 56 to 58, and 59 have all picked up. During the next card cycle the master card will pass under the #2 read brushes. Relay 59 holds until near the end of this cycle preventing either a reset or a finish signal. Inspection of the reader starting circuit on PX-11-307 shows that the starting flip-flop (65,66) is still set and that the starting relay is still activated so the reader immediately goes on to read another card. The relays *ich are shunted (by plugging reset control to reset shunt on the plug board) •ill hold the information read from the master card until another master card pa along. New information will be put into the other relays for each detail card, 8«4.6. Coding Cams
The coding cams are located at 6A and ?A on PX-11-119. They directly o^rate the coding relays located in the constant transmitter. See 8.3.1.
VIII - lfl
g,4,7. Reset Signal
Cam P4 produces the reset signal at time 12 in the card cycle. This signal wiU be sent to the constant transmitter (actually to the initiating unit) only if relay 60 is activated and relay 59 is not. Relay 60 is activated only when cards are in position at the #2 read brushes (see CR#2 at 3B, that is, continuous roll #2). Relay 59 is activated only when a "master" card ( a sard with a punch operating reset control relay 23) is at the #2 read brushes. 8.4,8. Finish Signal
Cam P3 produces the finish signal at time 9.5 in the card reading cycle. As with the reset signal this signal is obtained only if relay 60 is activated and relay 59 is not.
Br- 1
IX. PRIOTEB -iUD JBd GaHQ PCHCE
The printer causes eight, digits and as many as sixteen FU sign, «uchare stared far certain accumulators and possibly the master programmer to be punched on IBK cards. In the case of complements (which represent negative numbers) the printer relays cause the IBL punch to punch the true negative number and a corresponding sign indication (an 11 punch).
3/hon oporating continuous 1;. the IBU punch can punch a card in C.51 seconds. However whon starting from rest, the inertia of the punch- ing nechan ism makes the punching tine 0.82 seconds. The units of the DL.C associated with the printer (eight accumulators, say, and five decades of the M.P. do not have to wait while the complete punching cycle takes place but only 0.4 soconds. If tho punch is programmed before tho end of the first cycle to punch a second card then the two cards will be punched in 1.4 seconds. However, if the second program signal comes anytime after the first cycle is completed the punch essentially loses a cycle (bocause of the clutch dropping out) and the punching of two cards will take at least 2.0 seconds.
Thoroforo. if thoro is no nore than approximately 2,000 addition tines between printing prolans, the punch will punch almost 100 cards ?er ainuto. A small increase in the number of addition times between printing programs will cut this down to not more than SO cards per minute. It should be emphasized that while all these figures are valid at the time I Siting, they may vary with time, temperature, punch wear, and so forth.
The program control circuits for the printer are located in the Initiating unit. 'Then programed to print, the ZBU punch will start, the
IX- 2
rolays in tho printer will bo sot up by the static outputs of the various decades and PH units, a reset si^al mil C0Qe frflB ^ ^ ^ ^ jr.gr* control circuit, and the ?unch will complete the punchy cycle. The reset signal can be usod to continue computation in tho 3HIA0. Sinco the sot up tino of tho rolays is small compared to the tin* for p«ching a card this arrangement prevents undue waste of time vrhile the card is being inched. :Vhen the card punching cycle is completed an interlock signal coxs from the punch ta tho printer allowing the relays to set up anew provided mother print program signal came along in the meantime. This constitutes a mechanical interlock arrangement.
On the printer there are sixteen ■print* switches which enable the operator to print or not print any one of sixteen groups of fivo digit numbers and the associatod Fx," indication. Thero are sixteen coupling bitches v.hich mako possible tho printing of groups with ten or moro digits. Thcso coupling switchos servo no purpose when printing positive numbers. In printing nogativc numbers they take care of the carry over in tho proooss of taking the complements and also gang tho Pli relays for tho coupled groups.
Tho description of the printer will be given in terms of the following drawings:
Printer Cross Section P2-12-115
Printer Block Diagram PX-12-307
IBU Gang Punch PX-12-112
1>e discussion will be divided up. in the following manner: 9.1. Pro-ram Control Circuits. 9.2. numerical Circuits of the Printer. 9.3. IBLI Gang ^ch, and 9.4. Examples.
ix-s
jj PROGfUU* OOnTROL CIRCUITS
The printer program control circafts coaprisc most of two plug- in units in the initiating devioo (PX-9-104 and PX-9-105) and tho printing sritchis located on panol two of the printer. The circuits located in tho initiating device arc represented in block diagraia form on PX.12.307 (lwer left corner) or PX-9-30, and in detail on PX-12-115.
9.1.1 The Printing Switches I
The printing switches simply disconnect the power (+200 v line) to the digit and PM relays of each group. Thus, if the print switch for a particular group is set at "off", the relays of that group cannot pick-up iad thus nothing trill be punched in the corresponding position on the cord.
9.1.2 Starting Circuit
.Any pulse arriving at the printer program input terminal P (see PX-9-302) will (through the buffer 67) set the flip-flop (6S asd- 69). Ibis causes the driver 70 (which has its cathode at +20 volts, and has the storting relay as its load) to cone on, closing the starting relay (located in the printer panel Ho. 3). This flip-flop will be reset by a signal arriving from the punch through the buffer 72. (It can be rosot by an EG. sco Section 9.1.5.) 9«1.3 Reset and Program Output
After the printer relays have sot up. (these relays set up vrhen «» interlock con mokes contact and the starting relay is activated) near the beginning of the card punchin£ cycle (at cord time 11.2) tho reset «igncl will arrive at the printer fro* the punch. This signal passe. though the special pulse stondardizcr 61 and 62 (in unit F:L-9.105, s< ^li-iOT; for a description of this circuit sec Section 1.2.7). The
IZ-4
^ of this pulse standardly sets the flip-flop 64 and 65 and also ^ougb the inverters 63 provides a reset signal for the starting flip. flop described above.
The flip-flop 64 and 65 opens the gate 66 passing a CFP which i> the flip-flop 67 and 63. The output of this £l^flop ^te8 a ^.p [gate 69) which resets the two flip-flops passing through the transmitter 10 to 72, and appears at the printer output terminal P on the initiating nit front panel (see PX-9-302). At the tine of writing this report, farting with the punch at rest about 1900 addition times clapsod between
e reception of a program pulse at P and the output program from P .
A o
is time will probably vary with respect to temperature and age of the ach anong other things.
This double flip-flop arrangement is a synchronizing device. ace the timing of the reset pulse depends upon the mechanical operation the punch it will generally not be synchronized with the CPP in tho I*C. The output of tho gato 66 will be synchronized, but it cannot bo assittcd since the flip-flop 64-65 may be set at such a time that it ild pass a substandard pulse. If the Cr? passed by 66 is weak and does ;set the flip-flop 67-68 no harm is done for the next CPP (64-65 is : reset in this case) will be standard and -.rill set 67-68. The circuits Rising those flip-flops and their associated gate tubes are relatively •(the rise time is on the order of 50 ji seconds). Thus, if a CPP sets flip-flop 67-68, the gate 69 will open only in time to safely pass tho *ich arrives one addition time later, and tho output of gate 69 will !■ be a standard pulse. Tote that this program output occurs before c^rd punching cycle is competed (asking the punch starts from rest
IX- s
I at Op timo of writing this report this tin. wus approximately 1950
Edition tines).
9#1,4 The Interlock Cam^
The interlock can makes contact near the end of the punching cycle (card tine 13.3) and breaks near the Ft! punch of the next card cycle (tine 12.8) (seo tho time table on PX-12-307). This cm and a contact on the starting rolay (in scries) connect tho cathodos of all tho tubos in the printer to +20 volts. When this circuit is open the cathod— rise (see the 2K, 10 watt resistor near the starting relay on PX-1&-307) to ibout 200 volts. Since this is about tho same potential as the plates, my signal on the grids (and generally there will be signals on certain of the static outputs) will not cause any of the tubes to go on end set up their corresponding relays.
The printer nay again be programmed to print any time after the reset signal hat- arrived (see Section C.lvS). However, except for.;, te activation of the starting relay, nothing will happen until the end of the cycle which the punch is in; until the interlock cam makes contact. This furnishes a nechanical interlock arrangement. The second print signal cannot cause any tubes to conduct and relays to set up in the printer until the first punching cycle is complete. At tine 9.5 in the first eyele, tho holding cam breaks contact releasing all relays in the printer. « tine 13.3 the interlock cam nakes and (provided the start relay is activated) the printer relays set up in the new way and a second card is Punched.
Table 9-1 gives the timing of the printing sequence.
SA
Card
Time
L
IK. punch starts and relays^ set up. 13.6 Carry-over cam makes 5 Holding cam makes.
12.8 Interlock cam breaks (this turns off all tubes in printer and. thus, releases the accumulators and master programmer for other activities).
11 PL indications are punched.
11.2 Reset cam closes causing
1) Starting flip-flop to reset
2) Printer program output pulse to be transmitted. UtlhC proceeds with other computing
11.8 Reset cam breaks.
0
1 Digits are punched. to 9
9.36 Carry-over cam breaks.
9.45 Holding cam breaks
13.3 Interlock cam cakes. Relays will sot-up a^ain as soon as starting relay is closod. Note that the next printing signal may arrive any time._after the reset com breaks , that is, any time after, 11.5.
D Punch stops unless starting relay has been closed.
H- 6
Clearly, tho progressing in the EHUC must not bo arrcngod so
J^t a second print program input pulso arrives a* Pi before the reset
signal has been given out by the punch and the flip-flop 68-69 has been
reset. Hence, no pulso should bo supplied to the printer program input
until aftor a pulso has boon omitted from the printer program output P .
o*
.toy pulse arriving aftor the reset signal but before the end of the card punching cycle (that is, during the period 11.2 to D) will be remembered cd will cause the punch to continue and punch the next card. 9.1.5 Initial Clear
The only place that the initial clear gate is used in the printer circuits is to reset the starting flip-flop 68-69 (PX-9-104 in the ini- tiating unit). The characteristics of the tubes in these circuits ere such that whenev-r tho power is turnod off or turned on (in spite of the autoaatic initial cloar) tho starting rolay will be closed long enough to cause tho punch to food a card through,
9.2' THE KUfaERICAL CIRCr-ITS CF THE PRINTER
Of the sixtocn rolay groups, groups one and sixteen and parts of groups two and fifteen arc represented on PX-12-307. Assume that tho plugboard is so wired that tho columns (A. B, C. D. and E) correspond to tho first five columns on the IBS card. Suppose, furthermore, that the m indication for this five digit group is to be punched in column one or A.
There are fifty digit triodes in group one (actually 25 6SN7's) and three PiJ triodes. The grids of these tubes connect directly by a 51 line cable to the static outputs of the decades and PI! unit of an •ecomulator. Just one Pii line goes to the three grids of the PM tubes
IX-7
at
The tubes in each colunn are denoted by Ao to *Q, BO to B9, ^. that is. the second syabol icnotc£ tho ^ r3proSc;itcd ^ ^ tic boias «- "hc C^** of these tubes arc connected to the normally ^tivc outputs of. tho staccs of the decad. rings. Tho Pi! Hae in the w- goes to all fire- PL tuc,e (the tubes driving the carry-over relay C , tad tie -H r- lays il and Kj.
Ike leads fror. the enizx«r arrive at tha upper left corner of, PZ-12-3C7 These cieA-.ter leads go through transfer contacts on the relavs | acd :.g tc -he various digit levels in the five columns of relays.
..11 the ii^it and Til relays have holding contacts connecting fez to a line controlled by the holding cam. The holding can makes at the beginning of eke punch cycle (at IBii time 14.5, see Tablo 9-1) and breaks at the end of the cycle (at 9.45). These holding contacts cause acy relays -hich arc picked up by tubes conducting to remain up until the :nd or the cyclw. Thus, the printer tubes need to conduct only long enough tc safely pick up the relays. This deternines the length of contact made =7 the interlock can, (13.3 to 12.8) (note that if the punch stops between cycles then -ehe tubes begin to conduct at tide D = 13.5 when the starting relay is activated). Once the relays are picked up the tubes can be turned off by the interlock can and ail the units which conaoct statically tcthe printer groups whose print switch is "on" can then be released to participate in further computations.
If the interlock ce* has made contact and the starting relay is dosed, then one digit relay (in each column) picks up. corresponding to the actual nunber registered in the decade of the accumulator or master Prober. All three Pii relay; will pick uP together if the number i. aegetivo '
n- s
Suppose the nunber P1Z545 is registered in the decades and » jait oZ an arcunulator associated ruth group one relays. If the print pitch of troup one is set to print and the starting relay is closed (assuain^ the intor look cam is noting contact) then the tubes Al. B2, (3, 34 ana E5 >rill conduct Closing relays Al E5.
A? the card passes under the punchec , pulsc3 errivc from the Mittor OTer tv enitter lines. Since the above number tt^s positive all three Yl relays (CQ, L^ and Ji^) are unactivated. This seans that there is i connection frorr emitter line •one* through the transfer contact an ill, through the contact on Al to the transfer contact on Cl9 and on to the punch n-gr.et (via the punch plug board) for coluan one on the card. Thus, lien the one position on the eard is under the first column punch a signal free esittsr line "one" Trill (through this circuit) cause "one- to be punched in the first column of the card. The circuits for the above richer and for ::l237e ore illustrated by the rows in the following tables. In these tables (A) denotes that the relay is in the abnormal or acti- vated position while (IT) means that the relay is in the normal position.
The resistance-capacitance circuits found on the contacts of the carry over relays (and on one contact of the starting relay) ore to pre- vent arcing at the contacts. The protection is ncoccs-ry only on contact* Rich carry relative heavy loads, and not enly prolongs the life of the Wky but ^Tovides nore reliable operation.
In the case of the number ^2370. the minus indication .ill cause lly Cq to be activated which in turn (a^uMn; the eeupling switch U2 I set to -00 causes Cg to operate. Since the last digit is tero. relay f" (sroup 1 relays) will be. activated sfcich vrill D— ^ to operate.
n- 8a
|
Saitter |
Line] i |
1 Circuits ?oi r — — |
ABLE 9-2 |
|
|
The Number PI 2378 |
||||
|
FL relay J >lrit transfer f relay contact caatr.ct |
Carry-over relay trans- fer contact |
Line to punch magnet (via plug-board) |
||
|
1 2 3 7 8 |
I i r ! t |
hi GO : ai xa (IT) S B2 lil CO i C3 i & 00 .* 37 1 L2 (3) f * DB |
c1 00 c2 (n) c3U) c4 d0 c5O0 |
1 2 3 4 5 |
|
T^-3LE 9-3 |
||||
|
(Relays C0,Cg |
Circuits For The I'ucber K12378 (-87622) ,LL , and II arc new activated, C^ to C. normal, Coupling Switch |
|||
|
Enitter Line |
P.: relay transfer contact |
Di-it relay cert act |
Carry-over relay trans- fer contact |
Line to punch magnet (via plug-board) |
|
8 |
^U) |
Al |
Cj 00 |
1 |
|
7 |
4 (A) |
S2 |
c2 00 |
2 |
|
6 |
ha (A) |
a |
C3 (N) |
3 |
|
2 |
~2(A) |
D7 |
c4 00 |
4 |
|
2 |
-2 <~> |
S3 |
Cg (A) 5 |
Note: In the above tables 00 means the relay is in normal or unactivated position wnile (A) means it is in the abnormal or activated position.
IX. 9
Ibfi carry relays C,. C2 and C3 .ill not * activated so ^ ^^ ^ e<Dplenents with respect to ten (modulo ten) in the units and tens place ad with respect to nine in the other places.
It is essential that the carry over cam breaks before the holding 5SC does. If the holding can were to break first, then a string of carry orer relays which nay have picked up would bo dropped by the contact on re-lay C0 and since the carry over relays vhica have picked up arc connected is parallel the load hero would soon burn up the contact on C . Since the carry over Cum breaks first (at S.36 as against 5.45 for the holding cau) the contact on CQ will not be breaking any current.
There is one Pi. unit in each accumulator and there are two sets of T'u relays (one set with sach five digit group). Thus, to print ten digit negative numbers the p]* static output must bo connected to both sets of fc tubes. This is accomplished by the use of an adapter uhich connects the two Pi: lines to the one static output. In case of twenty digit opera- tion an adapter must bo used to connect tho four sets of PL tubes to the ?L static output of the left hand accumulator.
The adapters for the ten digit oporotion arc installed in the backs of the respective accumulators. This adapter (see PX-12-114A) is a plug and two sockets; the plug goes into the Fi- static socket (on the PiUlear plug- in unit) and the two sockets receive the two PI: lines of the two static cables. Tho adapters for more than ten digit operation *ro best installed in the printer (behind front panel So. Z) (those for ton digit op.ration could be installed hire. too).
To moke it possible to print the actual numbers registered in certain decades (regardless of sign) there is - ^ound lug on the printer
EC- 10
?lttSS ^ich normally connect to the static P,' leads. ^other adapW (m ^ with a *mp~r inside, see PX-lfc-lUB) used here pounds the grids of j^Kt-bu. XM« prevents them fran conducting; if the grids are allowed t0 .float- the tubes may or nay not conduct. Such on adapter nust be used. ;or example, whenever printing numbers from decades in the mastor programmer.
9,3 TE3 I5M G.tfiG PUKCH
The iaii ..ang punch will be described in terms of diagram PX-12-112. This punch \ras constructed in the following manner: An unfinished standard -bv% sunuary punch -.-as removed from the assembly line and certain details. such as cams and column split relays .-.'ere added to malce a punch for use lith the E17IAC. This means there ir come unused apparatus in the punch; for oxanplo, there is a sot of control roading brushes and the continuous roller is in for the regular set of reading brushes. This also explains fa there arc shunts on some relay contacts. The master-detail switch located on the front of the punch simply acts as an cn-off switch for the punch magnets ('on* corresponds to ■master*). 9.3.1 The a-c Circuit
The a-c connection is normally plugged to the outlet on the bottom of panel two of the printer. Power is furnished to this outlet only ucn the EM..C is turned on. Cutlets on all other panels except ?~-iel three of the constant transmitter have ?over all the time. Tans, if it is desired to op-rate the punch without turning on tho EBIaC ono of tte outlets of one- of tho other printer panels may bo used.
:Vhcn the a-c power is turned on H.D. relays C. 2 ** Ho. 3 close tarting the aotor --encrator and closing the 40 volt d-C circuit. Tho
n - 11
reen light on the front of the punch Indicates that the aotor generator is operating properly. The drive motor is started by the closing of con- tacts on K.D. relay Ho. 1. The pick up coil for this relay is in parallel Ith R9. R9 is picked up by a contact on RIO and another Contact on RIO operates the clutch. Thus, relay 10 is the starting relay. S.3.2 The Starting Circuit
There are three card lever contact*,
1) Die card lever contact (Di» CLC)
2) laagarine card lever contact (iiag. CLC)
3) Brush card lover contact (3r, CLC)
shich activate relays 1. 3, and 7. Thoso card lever contacts detormine if the cards are being fed in properly. There is a die context which deter- mines if the punch die is in proper position. If tho die contact is open, neither the start key on tho punch, nor the starting circuits of tho SIAC rill operate the punch. The various card lover contacts arc by- passed by the start key on the punch. Thus, it can ba used to feed tho eards into position vrhen they are first put into the magatinc.
If the magazine runs out of cards the punch will stop. If the starting relay is closed the printer relays will pick up and the punch will operate -.he uoaent new cards are placed in tho raaguiine. The operator ehould hold down the stop key ..hen rutting now cards in this case. Otherwise, pa punch ;r.ay start boforo the cards arc firmly seated and nay fail to toad tho first card.
To start the punch, the E.IAC conpletcs the circuit fro* termi- aale one to eleven. This, throush contacts on relays 1 and 3, closes R23. A contact on R23 causes RIO to close. Contacts on RIO cause R9', relay
IZ - 12 l no. I. and the clutch to pick up. Relay 9 ^ -^ ^ ^ . ^ L by RIO and by the continuously running can (C.R. Cam)# Relay M ^ L is held by cam ». Thus. «hen the starting relay is closed in the printer, relays 5 and 10 Pick up and hold until the end of the card punch- ing cycle. At that tine they drop out as does H.D. I7o. 1. The clutch drops out when relay 10 drops and the drive notor coasts to a stop.
Note that the operator oust use the initial start switch to feed sards into position when Starting, since with -^ards only in the magailne, the SIIAC starting circuits vrill not operate.
A card stacker snitch opens the starting circuit when, too many ards ere in the stacker. '.Then the cards zre relieved the machine will continue to operat- in the proper uanncr. 9.3.3 The Colann Splits (PL Circuits^
The pick-up coils of tha colurm split relays are located at 5C on PX.12.112. These relays are activated by can ?2 during tho tiae that L 11 and 12 positions of the card are pasclng under the punches (actually, free 13.5 until 11.6). The relays act as a sixtcen-polo, double-throw switch (see tho contacts at 7 and 0 a and j) and connect the punches (via plug-board connections) te the clans indication terminals (at 80) during the 11 and 12 positions of the card and to the computer result exit terminals (80) during the rest of the ca d cycle. This oakes it possible to punch a P.. indication and a digit of a number in the same coluan. 9»3«4 The Punch Garnets
The circuits te the punch nagnots is completed by contacts on i*|« « to 56. These relays are activated by a circuit through the
n - 13
Ler-dutail arlteh (with switch setting on Wer-), a normally ciOSed cotact or. R14. and caa P12 (aakes at 14.3 and, creaks at 9.3).
9.3.5 The Epitter
The emitter is located at IOC. It turns in synchronic as the tirfptsses under tie punch a^gnets. th^t is, the eaitter Bonnecte to line 3, for example, .fhen position three is under the punches. If tho circuit is completed froa ccitter line three hack to the punch cagnets -Jsen thrc- will he punched.
9.3.6 The Plugboard
Instructions for plug-board connections appear on ?2~'}Z~305. Tho eighty-digit outputs appear on eighty hubs on the plug-hoard. The e ighty punch magnets appear on eighty other hubs. Thus, information can te rearranged on the card in any desired nannar.
X-l
X. UASTHt PROGRAMLER
The master progranner occupies two panels. The two panel* are , practically identical in function and in appearance. The Block diagraa i ?^-30, refers to the left hand panel; however, by changing some of the
teminology, it can refer equally well to the right hand panel. Thus, in the ' follwing discussion only the left hand panel will be considered. In the left
tad panel the decades are numbered from 11 to 20 (reading from right to left j as in an accumulator) and the steppers are named A, B, C, D, and £ (from Left . to right). In the right hand panel the decades are numbered from 1 to 10 ; ad the steppers are named F, G, H, J, and K.
10.1. INTRODUCTION.
The Master Programmer contains only program circuits, there being so numerical or connon programming circuits. The program circuits will be iivided into two types, npjnely, stepper circuits and decade counter circuits or d;cade units. The decade counter circuits are represented on PX-8-30i by the ten rectangles along the top of the drawing. The five steppers are represented J! the rectangles along the bottom. The decade counter circuits are divided into groups, each group being associated with a steppor. To give flexibility Leade sgsociator switches arc provided which change a d.cade circuit frco one foup to another.
to.2. decade a»;irrai circuits.
10.2.1. Decide ron^. The decade rings used in the master programmer are ten
X-2
| ring counters located on plug-in units. Tha clear inverter (tube 1) aalso located on the same plug-in unit. The pulse standardizer and the K circuits associated with the ring are on a separate plug-in unit. In ftft, for each pair of decades the pulse standardize^ (21-23 and 25-2?) aod erry circuits (2/,, 28-31) are on one plug-in unit.
Provision is made for making static cable connections to any decade ling of the master programmer. This would enable the operator, for example, io register an independent variable in certain decades of the mster programmer d to print it whenever desired.
The normally positive outputs of the stages of the decade ring go to it respective positions on the six decade switches. The common connection of eth switch connects to the grid of the inverter tube B 41-A3 for decade 11). If there is a coincidence between the setting of sny decade switch and the ::sition of the decade ring the corresponding inverter will be turned off. Since Ol the switches are illustrated as setting at "7" all the inverters eule b«. turned off if the decade ring was stepped to stage seven.
The carry circuit. Whenever a decide is stepped to stage "nine" fc static output causes gate 26 to open. If another pulse is fed into the m stsnd-rdizur the ring will step to zero and a pulse will pass gate 28 Ipte 2k for even numbered decrdes), go through the inverter and buffer 30 I thence to an association switch or, in some cases, directly to the input of *e pulse standardizer for tlie next decade to the left.
The carry circuit is spread over p^rts of three plug-in units and, I, necessarily has a very poor time constant. Actually, the rise tine i
X-3
I circuit comprised of stage nine of the ring and gate 28 on a separate plug-in unit (four times the tine constant) - approximately the time for the signal to reach 97* of its maximum amplitude is on the order of one-half an Edition time. Thus, any sequence of digit pulses which would produce a tarry-over cannot be fed into the decades of a master programer during any me addition time. There are other situations (see the discussion of clear circuits below) where digit pulses cannot be fed into these decades.
The clear circuits. This ring is cleared by a CPP passing gate B44, for example, and turning off the clear inverter (tube 1) on the decade plug- in unit). This clear circuit is operated either by the initial clear gate ariving at tho buffer B45, say, or by the operation of one of the coincidence gates (B, C, 48-50) in the stepper circuits (E). Generally, one of these coincidence gates will conduct when there is a coincidence between the position «f the stepper ring, the settings of a number of decade switches and the position of the ecrresoending decade rings.
Since the clearing is accomplished by a CPP passing gate B44 (in decade 11) the decade cannot be stooped by any number of digit pulses (arriving over the direct input lldi) wliich will step it past a coincidence position. Ms restriction is not because of the time constants. Actually, for the clearing to take place the ring must come to (and stay on) the coincidence position (that is, the position corresponding to one of the decade switch set- tings) so that gate 63 is set up at pulse time 17; and pulse tine 17 is rone I (at least seven pulse tines) after the last digit pulse arrived. In fact.
X-4
.; yt Eulscs shouW not be used to step this ring to a coincidence portion.
Ibe rise time of this clearing circuit, (as *ell as the stepper clear circuits) j i, an the order of one-half an addition time (10 pulse tines). Thus, the circuit j ^ be expected to operate satisfactorily only when stepped to the coincidence
position vdth a program pulse (CPP). Note that the time constant of these
circuits vary considerably depending upon the positions of the association
switches and the stepper considered.
Note th'-t there is no provision for delayed carry-over (as in an
accunulator). This means that two associated decides cannot be stepped siaul-
taneously in a manner which produces a carry-over.
10.3. THE STEPPT-R CIRCUITS.
15.3.1. The stepper ring . The stepper cont?ins a six stage ring located on a plug-in unit. On the sane plug-in unit is a pulse stc.ndardizer and a set of inverter tubes connected to the outputs of the ring. All of these circuits use the tub^s numbered from 21 to 32. The set of outputs of the ring which go through the inverters go to two sets of six gates each, B and C IS to 50 and the gates nrnbered 61, 65, and 69. The other outputs of the stages of the mg go to the respective positions on the stepper cle:r switch. The coercion terair-1 of this switch goes to gate BUI. When B47 is open any pulse driving L the inverter 61 and buffer 62 will clear the stepper back to stage one, The stepper will clear to stag* one in the following cases:
a) When the initial clear gate is applied, gate C47 opens letting through a CPPl ^ich turns the inverter 046 off clearing the ring.
b) A pulse arriving over the clear direct input (cdi) turns the
X-5 lifer Bi»6 on and the inverter C46 off.
c) If the stepper is set at stage five and the stepper clear .itch is at five (as illustrated) the gate B47 will be open. A pulse passed tygate 63 or from the buffer 61 on the stepper direct input (di) will turn the ■ inverter 61 off and the buffer 62 on. This will cause the inverter B^6 to go
off erasing the gate tube Btf to conduct. This in turn causes the clear inverter ; &6 to go off and clear the ring.
The stepper clear circuit. The stepper clear circuits will not jperste in one pulse tine (the rise tine for this clear circuit is about one half an addition tine).. This means that the- stopper ring can be stepped with digit pulses only if the ring is not stepped onto the coincidence position (that is, onto the stage corresponding to the setting of the stepper clear witch).
The stepper direct input. a direct input (through buffer 61) is provided to step the stepper ring. In this case the associated decade units ring is not stepped and no output program pulse is obtained. Note (above) the restrictions on the kinds of pulses supplied to this input.
The stepper input. The flip-flop (66,67) and the associated gate 69 his a tine constant approximately equal to that of the slow buffer output of a transceiver. This means that this input (% for example) must never be pulsed later than pulse tine four. That is, it can be pulsed by a CPP, 9P, 1P# 2Pf <* I; but not by If, liP, or generally by any digit output of an accumulator.
Note that if h a*d Ecdi, for example, are pulsed simultaneously, the tepper will clear first and the output pulse will be from E^o.
i:.3.2» 22!£ Pr°grr-C transmitters.
In the lower right h.nd corner of the rectangle (FM-jOt) containing & stepper circuits there axe six gates and six standard transmitters. One of Le gates will be open depending upon the position of the stepper ring. ' Any pOses arriving from the buffer 70 will be transmitted through one of these fennels. In the illustration the stepper is setting at stage one so any pulses free 70 will be transmitted through the left hand gate 61 and will appear on ftj output terain-J. E^o. Note that a lead conies fron the master programmer cle»r (UPC) to all these gate tubes. Inspection of the cross section PX-8-102 i3»s that this lead goes to the screens of these gate tubes (6SA7's). Whenever the initial clear is activated a relay located in the initiating unit changes these screen voltages from +150 to 0 volts. This blocks these gates, that it, even if a signal arrives on both control grids the tube will not conduct. is explained in section 2.1.2. the effect of the initial clear is to clear decades tack to their first stages and let the program circuits run out their sequences. Ey program jumpers various program controls in the machine may be connected in a sequence ti~« will take several hundred addition times to run oat. These sequences cay be tied together by the master prograoner so they wild take a v-ry long tine to run themselves out or even repeat indefinitely. Ic prevent this tying together and, thus, make the time for initial clearing reasonably short the output gates in the master programmer are blocked in this taer. A period of about one half second will be sufficient (including a fety factor) for any possible sequence set up in the other units of the HOAC I run cut, therefore, the initial clear lasts for approximately one half second.
X-7 1D.3.3* Hl£ Program receiving circuit.
The input program will ordinarily come in by the terminal El causing the buffer 65 to go on setting the flip-flop 66 and 67 . The output then ||akes £ positive swing opening gate 69. The next CPP is passed resetting the flip-flop and turning off the inverter 68. This causes the cathode fclloner 70 to go on giving a positive pulse to the grids of the gates $1, 65, and 69. This also turns the buffer A43 on giving a negative pui3e to the pulse standardizer of decade 11»
As described above, 10.3.2, one of the six gates (61, 65, 69) is open depending upon the position of the stepper. Thus, for every pulse put into Ei I pulse is sent into decade 11 and a pulse comes out of one of the terminals Lc to E/0. one addition tine later.
Pulses fed into Edi cause the stepper to step, and pulses fed into lldi cause the decade to step. Neither of these cause any pulses to be given out at the output* E_o to E^o.
10.3J*. The coincidence gates. The coincidence gates are the tubes B and C 48 to 50 for stepper E. Whenever any one of these gots a signal on both grids the inverter 64 goes off and the gate 63 is opened. This passes the next C?P to the inverter 61 and the buffer 62. The output of 62 goes to the pulse standardize 21, 22, and 23. stepping the ring and it also turns the inrerter Bfc6 off. If the gate B47 is °pen the clear signal from C46 lay overrides the stepping signal fron the pulse standardizer and the ring dears back to stage one. Also, a pulse on the clear direct input (cdi, Bt6j °r a CPP passed by gate C47 (when initial clear is activated, "ill « i« «ith adequate safety factor) override any stepping signal.
X-i
The output of the stepping gates also goes to the clear circuits in p decade counter causing the decade to clear back to zero. Again, this clasr Li overrides any stepping signal*
Stepper E, with the decade associates switch for decade 12 setting a illustrated, has only one decade associated with it. Consider stepper D. itfs stepper has decades 12 and 13 associated with it. Looking at stepping r-te E/3 it is seen tnat aDe °* tne grids connects to both the inverter D41 R through the D-E associatcr switch, to the inverter Cfcl. If either inverter is conducting the grid on E/JB will be sufficiently negative to prevent it from conducting. This constitutes a multiple coincidence arrangement. That is, in rder for Ei»8 to conduct three inverters nust go off, namely, CAl, DU., and 32 in the stepper ring unit. Consider stepper C. If five decades are anocl- tted with stepper C then in order for the stepping gate GlS to conduct the inverter in the stepper ring unit imist go off along with the five inverters in the respective decade units.
Steppers A and F nay be used without any associated decades.
Ihen the A-B association switch (or the F-G) sets at B the screens of the
coincidence gates (L, K, (3-50) are switches from *150 to 0 volt.. This
prevents any of these gates from conducting and, thus, gate 63 neve
this aeans that the stepper ring can be stepped only by pulses introduced over
the direct input. The sWpper clear direct input functions as before. A*
pulses arriving over the pr.graa input will be transmitted over one of the six
outputs depending upon the position of the stepper ring.
i. «., the above manner Any of the other steppers may be made to operate in the
. , th.t the only difference k7renoving the gate 63 in the plug-in unit. Note, tn.
x~9
jjtbe operation of these other steppers (as conpared to A or I) i« that jjrtain decades will count the pulses coning in on the stepper program input. jese decades will clear at positions depending upon the settings of the decade etches but there will be no corresponding change in the stepper position, £a clearing could be prevented and, thus, the total number of program j-ulses canted by removing the coincidence gates (D, E, 48-50, for example) instsad af gate 63.
10,4, ASSOCIATION SWITCHING.
All the decade units are exactly alike, and the stepper units only differ with respect to the number of decades that can be associated with each 3ae. PI-8-304 shows that decade 12 can be associated with either stepper D W E. Decade H can be associated with either C or D, decade IB with either B or C, and decade 20 with either A or B. When deeade 20 is associated with stepper B then stepper A has no associated decade (see above)
The decade associator switch is a nine pole double throw switch. The
six poles on the left handle the outputs of the inverters associated with the
decade switches. The seventh pole takes care of the clear circuit, the eighth
the input to the next decade on the left, and the ninth the input of the decade
to be associated. In the case of decade 20, since there is no decade to the
left, the eighth pole takes care of the input to decade 20, and the ninth pole
is used to change the screen bias of the coincidence gates.
. a» m As illustrated this Consider the associator switch for decade 12. as h*u»
decade is associated with stepper D. The following table illustraf kppens for the two positions of the associator switch for de
TABLE 10 . 1
X-10
|
Associated with D |
Associated with E |
|
|
Outputs of the inverters C41 to |
Go to stepping gates E and D 48 to 50. |
Go to stepping gates B and C 48 to 50, |
|
Decade clear input (to C45) |
Goes to the output of the stepping gates E and D 48 to 50. |
Goes to the output of the stepping gates B and C 48 to 50. |
|
Input to decade 13 |
Goes to the carry over circuit of decade 12. |
Goes to the buffer a*4 of stepper D. |
|
Input to decade 12 |
Goes to the buffer A44 of stepper D. |
Goes to the carry over circuit of decade 11. |
Thus, when decade 12 is associated with stepper E, decade 11 acts as a units decade and 12 as a tens decade in counting the number of program pulses coming in at the terminal Ei. Therefore, the two decades can count as sany as 99 pulses coming in at Ei. When decade 12 is associated with stepper decade 11 acts as a units decade in counting the number of pulses coming in * 1^ and cannot count more than 9 pulses. In this case decade 12 acts as a units decade in counting the number of pulses coming in at Di.
Consider stepper C. If both decades 14 and 18 are associated with stepper C then the five decades ( 14 to 18 ) can count as many as 99, 999 pulses arriving at terminal C^.
XI. 1
II. TEE HUSi.ISSICN SYSTEL AID SPECIAL DEVICES
Thi. chapter contains a description of the digit and progra. trunks which carry the pulses representing digits or program signal. free one unit to another. aIso various special devices such as shifter.. deleters, adapters, static cables, and so on, are deseribod in thU chapter. \
It is necessary to transmit pulses representing digits or pro- gram signals fron one unit of the EIII^C to another. Furthermore, thi. aust be done in an entirely different manner for each new problem that i. put on the Ei<L*3. Thus, the interconnection systems must be very flexible. For this purpose trays and jumpers are used. 11.1.1 Travs
A tray is essentially an eleven wire transmission line, capable of being connected to other trays and to the digit terminals and program torninalc of the various units.
Each tray ic eight feet Ion-, nine inches wide, one and a quarter inches deep, and open at the bottom. It contains eleven wires separated fron each othor by metal shields. The trays are placed on top of one another so that they will actually be shielded on all sides. Each tray is equipped uith outlets on each end so that it nay be connected to other trays by seans of junipers. It also has outlets every tvro feet of its length so that it nay be connected to the program and digit terminals of the various units of the E7I*C. These outlets are of two kinds,
set
xi. a
^dif-it tray, - shown in drawing PX. 4-29 has «w v
•-zy.has for eaCh outlet
, trelve-contact plug (eleven wires and ground).
J. program tray, . shown in PZ-4-101. has for each outlet a of eleven two-terminal plugs (one wire and ground). & each end of the jrogran tray is a twelve contact plug to facilitate its connection by a •hepc-r to another program tray.
Those trays are stocked on the front of the various units of the SHIaC, sono above and socio below the program control panels. Gcnsrall-, zx program trays will bo placed below the control panels and the di-it tr^ys will be placed above. There is room for about twelve, trays to fit -hove ~nd twelve: below the control panel of a unit, although a =aci smaller number will ordinarily be sufficient. 11.1.2 Jumpers
Cables cr jumpers are used to connect the trays tc the digit
iersiaals and program terminals. There are two kinds of junpers^ QneT
a trcgran jumper, consists of a single wire and ground and is used to
tray :nc=t a socket on a program to a program socket on one of the units.
fte other, a digit Jumper, has eleven wires and a ground and is used to ersnect an outlet on a digit tray to a digit t-rainol of a unit. This list type of junper is Jsc used to connect trays together. "• 1« 3 Trunks and jLlncs
A single ./ire und ground, running through several program trays. J5=?,re or pr.grom cables ~nd thus connecting a number of pro&TJi
^- 1 -f eleven wires »als tc one another, is called a program line.. - =-* -1
~a <+• -i-s 2nd running a* ground used tc transmit a ten-digit nuaber end it- -130
^-"ugh several digit tr&yt. jumper- or cables, is c-Ue ^ J -,
n-s
One set of digit trays (9) „e connected to£ether to for* the cycling unit trunk. This carries the various ?ulse8 ^ gat9g ^^ by the cycling unit around to the various units of the BIIaC. Sine tra are sufficient hore einco the printer does not connect to this trunk. See PX-9-307.
11.1.4 Load Boxos
Each viro of a digit trunk and each program lino has one load rjsistor connected to it. These resistors arc assembled in box-s, (sec PX.4-103) and one hox is to bo plugged into an otherwise unused outlet at the end of one of the end trays of each set connected together by jumpers. Ac explained in Section 1.2.8, this nakos it possible to have the flexibility of being able to connect varying numbers of digit and projren terminals to the trunks and program lines.
11.1.5 Load Units
The pulses and gates transmitted over the trays must have rise times better than 1/2 microseconds. This sets an upper limit to the value of the tine-constant, RC. vhere R is the equivalont resistance of th; transmitter, and C is th- capacity of the trays and interconnoctor Bfclas. The value of R has been made low by using two triodes (pentodes connect,! as triodos) in parallel, with the load in the cathode circuit. To lo*er it further '.rould require more tube- and appreciably more power. It is therefore nscess-ry to design the trays and connecting cords so that the maximum C to bo driven is never larger than 5.000 nicromicr* farads. Capacities from one line to another must be kept to a Action of the capacity to ground, in order to avoid cross-t-
XI-4 Tho flexible shielded cable which is available for uso fa,
sjciag interconnection cables has a capacity of about 30 micromicrofarads L foot. If each cable is three feet long, and 30 such cables are used a a given trunk lino, the capacity thus added nay bo of the order of 3500 oafd. This leaves no more than 1500 nafd. capacity for the trays iad their short interconnection cables or jumpers. If eight trays arc iscd. a tray and its jumper must have a capacity less than 300 mfa. Since an eight foot length of shielded cable would have more than this, it is not possible to use this for running digit trunks and program lines the length of the E;*I.£. Special coaxial lines would not only be expensive, but would excessively complicate the job of connecting in ti9 sockets v/hich are to occur ovary two foet.
The tray design v/hich has been adopted is nearly equivalent to a coaxial lino with convenient oponings ov^ry two feet. The Siii-ld- isg is not perfect, but cross-talk is reduced to less than five per cent for oven the worst combination of conditions. The maximum cross-talk then amounts to a two-volt pulse, vmich can have no effect sines it is t;Flisd to the grids cf input tubes biacod at -20 volts, with cut-off tt -8 volts.
Clearly, there cannot be too nany jumpers connected to a particular digit trunk or program line or else the capacity given alove *ould be 2xceeded. To assist the operator in detrraining the maxiaua safe loading the following term is introduced.
One load unit is a capacity of 160 micromicrofarads. The folio-ring devices './ill each be called one load unit:
XI . 5
(1) Ag^ or d^lt cable. * the cable i8 only thre, , fact long, it wfll account for about 90 mmfd. The balance Is allowed » ee portion of the circuits which will be internal * the vutlaan pisel to which the cable is connected.
(2> k tray and lts g£gS i»5E££ ^ connecting to the next tray. The tray accounts for about 120 mmfd. and the balance easily accounts for the junpor.
The standard transmitters usod on the regular program and digit outputs (not certain multiplier and divider outputs) are designed totransn.it into a line containing not more than 60 load units. Actually pro-am transmitters can transmit into as many as 130 load units trith the oiutl lil safety factor^ 11.2 DELETERS
A deleter is usually used to delete non-significant figures,
and is therefore v.sed on the add or subtract output digit terminals. Various types of deleters and the connections cade in each are illustrated en drying PX-4-109. A deleter merely open-circuits the lines corres- ponding to unv/anted digits. Hote that when a deleter is used on the output cf an accumulator the significant figure switch should be set _ to the numb-.r of figures not deleted. In this case, the subtract pulse will be sent out over the line belonging to the significant figure furthest to the right, next to the deleted digits. Thus, the subtract ?ulsc is not deleted.
11.3 SHIFTERS
A shifter is used to shift the digit lines to either the fight or the left, and is placed on the input terninals of an ac ktor. Thus, a shifter is generally used to multiply by powers of Jfc
;rr — r V *^» epp as eaapavi to
'The reason for this is the difference in shape of the W the 10P.
XI. 6 j„ example of a +2 and a -2 shifter are given on PX-4-104A,
A.,* snifter. A ♦ shifter multiplies by positive integral powers often. In the case of a +2 shifter (PX-4-104A) any pulses arriving over the units channel (terminal 1 of the socket 8S«) goos to terminal 3 (hundreds) of the plug (P). The plug is inserted in the input digit teraia&l of the accumulator. ".loto that terminals 9 and 10 of the socket are cot connected and that terminals 1 and 2 of the plug are connected to ground. This grounding prevents the grids of the corresponding input rites frou picking up any cross-talk or other noise.
A - shifter. The - shifter muitiplios by negative integral powers of ccn. In this cat©, the unused terminals of the socket (soo PI-4-104A) are not connoctod hut the unused channels of the plug "F* cust be fed -.rith nine pulses in case of a negative nusb.r in order to give tk proper complement. Thus, if 1C99430 is multiplied by one tenth the result is 2J999430. Thus, the Pli line (terminal 11 on S) must be connected to tcrninals 9. 10. and 11, on P in the case of a -2 shifter. An adapter of this type must be used on the input to an accumulator since otherwise do K transmitter would hare to drive three different digit linos instead =f just on. digit line and three Lrids of the input gates to the accumulator.
U.4 PULS2 AMPLIFIER U1IIT
A pulse amplifier unit consists of eleven standard transmitter. *ich interconnect to trunks. Since the buffer unit transmits in only
"» direction, tvro units would be needed to completely intcrcoxucc trunks, m counting the load units en a p-rticular digit trunk. I «w?lc. the inout to the buffer unit counts as only one
n.7
siflCi the buffer unit contains its eU tTuitsmlttws none of the lo.d unit. af the trunk tr-ns.uitted into count ^ fcein^ on the first trunk Thai these buffer units -How the operator to practically double the nunber- cf units which a-j be connected to-cthar via u digit trunk systes.
rae buffer ulta ~r* desired to sit on top of a g^ of ^ ?x cr diQit truys. The unite contain their wm transforaew for snplyiss the neater voltages. The d-c power and the a-e power for the haters is furnishod by sockets located near tha floor between accucu- ktcrs nine -nd ten -nd bctww.n accumulators fourteen uid fifteen.
a block diegrun of ^ buffer unit is given ;n drawing FI 4 301.
U.5 STATIC CUTFOTS
Each decade and PL unit of every accumulator has a static output socket, accessible froti the back. To avoid capacity loads on the counter circuits, a lar~e resistance is placed in series witn each static output Iks, T.is tkse constant thus introduced into the static output circuits is la.-£e enou,eh so that one addition tine must be allowed for the opera- tion of other circuits from theso outputs, Howc7»r, because the system Is i static one. there is no cross-talk problem, and unshielded rircs mU used for the static cables.
Static cables are us^d to interconnect units in the followinc, eases:
(1) lo connect the multiplier and multiplicand accumulators to 4e tultipliir, see ?;;-6-30l.
(2) To connect certain accumulators and perhaps certain of the Easter pro^-anner to the printer, =ea PX-12-304.
(3) To conneet the PL unit of the operator and denominator tosdators to tho divider, soo FX-10-303.
PX-4-111 rho^c the wiring connections of ft 3Utic Mble>
11.6 SF2CLX DEVICES
11.6.1 Special Program Jucrpcrs
As -roll as tic regular program ji=?-re described in Section U.1.2, th^re arc loaded -prozran .jumpers and I -.ro^ras .ins-TCrs.
,. loaded program jumper is to be used -rb*.n connecting one •poxz.: ojtp'it directly to- another projra^ input. The junper is physically chiTaJteriied by having on extra long ">lug at one end which contains the Kilt- in load resistor. Such a jumper must ne~er be used in connection •it1" a program line vhich enters a tray sysxes ^hich has its ora load
te.
;> T-pro^raa juaper is a jumper rrith three plugs attached. It is ssed to connect tvo nearby program terminals (input or output) to the J6=3 prolan lino. It has no built-in resistor so on^ conne-ction must ?toa prolan tray system which hus a load box. pL 5. 2 Accutjulat cr_ Int ore onn e c t ion Cables
There ar* social int er connection e^I.s and load boxes for » 'ith accculators -.rhich dct.rminc vhcthr they act as ten digit
+--r— v di it a^ca-'-lator. Kftaulators or whether tvro ^ccuaulators eer — - **•-" * c
?« -■ description of these c-bles, see rX-5-301.
!1-'-.3 :.--lti-,li.r Int^rconneotiQn_C^bles
, • i - f«.ll into usro classifi- Tht &ultipli*r interconnection c— 1-* r«-^ «
o its associated btioas. Fi—t. thort, that connect the ^ultirl^r z '" "
XI. 9
j .ccunulators, *nd secondly, those that interconnect the three attltiplfcr
; panels. In the latter classification, damage to circuit elenents and
! short circuits across the pe.rer supply may be caused by erroneously
plugging a -.able into the /rong cocket. This possibility is avoided by
i removing prongs from plugs, arid filling corresponding socket holes
' (^ere not used) in such patterns that erroneous connections are iapoaaihla.
Reference should be made to the following diagrams!
Interconnection of High-Steed
Multiplier vith Associated PX-6-311
Accumulators
Static Output Cable PX-4-111
.Accumulator Interconneetor Cable (liilt.) PX-5-131
Cross reference should be made to the Operator's i-anual, PI^-304. 11. 5. 4 Div ider Interconnect ion Cables and Adapters
Since che divider and square rooter serves largely to progran its associated accuuulators , those inter connect ions which oust be established between the trio units mentioned for tho purpose of cooauni- B*tiag program instructions are made through cables as illustrated on FX-10-307, which drawing raakes further reference to special cables and adaptors used.
Cross reference should be mado to tho Operator* manual, 71.10.307. U.6.5 Function Ta^le .^dapt.rs
In or^.r to disconnect the 9F gates (3' and I/O fron the ■WtamiH^ crunk line carrying th. 9P. and to connect thrsc gates t<
n-io
L line carrying the CPP in the Bame trunk, an adaptor (PX^-119) is used. ' This adaptor is connected where the synchronizing pulse trunk plugs i^o
the- baric of panel Ko. 2 of the function table. |ll.6.6 Other Adaptors
The remaining adaptors may be classified as; 1) special digit adaptors, 2) digit-program adaptors, and 3) printer adaptors.
The first group, consists of adaptors which combine shifting and deleting characteristics and are shown on PJU4-117.
The second group servos to make possible the use of digit tray* is program trays. Each adaptor (there are 50) consists of a box with a 12-prong digit plug at one end, connected to a mounted group of 11, two- oper.Lng program sockets at the other. These correspond to the 12-prong sockets in the digit trays, and the two-prong plugs on program cables.
The third group consists of two adaptors. Adaptor A (PX-12-1M) eoai:cts the- static output of stage U (of the printer interconnection [cable to accumulator or master programmer decade counter stages) to the L lead in c-ch of two static output cables. Adaptor B is ustd when no connection is desired to tho Pfci lead in the static output cables. Adaptor B is also shown on PX-12-114.
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